VSIM HLS error due to __ihc_hls_* DPI C/C++ Calls

[JShel4]

Hello,

Has anyone seen DPI call issues when executing msim_run.tcl for the HLS example designs shipped with Intel Quartus?

I installed 18.1 (and later 18.0). Tried to "make-fpga" in counter example design. It passes. Later realized that the default script only compiles - does not run the simulation. So, I ran the ModelSim simulation by myself and ran into issues because it cannot find some of the imported DPI C/C++ calls in the simulation models. For e.g.:

# ** Warning: (vsim-3770) Failed to find user specified function '__ihc_hls_dbgs' in DPI C/C++ source files. # ** Warning: (vsim-3770) Failed to find user specified function '__ihc_hls_register_component_invocation_info' in DPI C/C++ source files. # ** Warning: (vsim-3770) Failed to find user specified function '__ihc_hls_get_stream_obj_ptr_for_component_interface' in DPI C/C++ source files. # ** Warning: (vsim-3770) Failed to find user specified function '__ihc_hls_stream_front' in DPI C/C++ source files. # ** Warning: (vsim-3770) Failed to find user specified function '__ihc_hls_stream_read' in DPI C/C++ source files. # ** Warning: (vsim-3770) Failed to find user specified function '__ihc_hls_register_stream_data_rate_info' in DPI C/C++ source files. # ** Warning: (vsim-3770) Failed to find user specified function '__ihc_hls_get_stream_obj_ptr_for_component_interface' in DPI C/C++ source files. # ** Warning: (vsim-3770) Failed to find user specified function '__ihc_hls_stream_ready' in DPI C/C++ source files.

These warnings lead to the main_dpi_controller throwing fatal error with trying to "run -all"

Any help will be super appreciated! Thank You!

[MuhammadAr_U_Intel]

Hi,

This is expected, by default when you compile the example with command

make test-fgpa (for linux) or build.bat test-fpga (for windows) it should test simulation script and later running the executable file will run the simulation.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/hls/ug-hls-getting-started.pdf

Page 13

4. Run the build.bat test-fpga command. The command compiles the C++ source code to a hardware executable and then runs a simulation of the generated HDL.

Expected outcome after you run the build.bat test-fpga command:

• The console displays the command it uses to generate the testbench binary and the contents of the project directory. For example,

i++ -march="<FPGA_family_or_part_number>" <source_files> -o test-fpga.

• The HLS compiler creates a .prj directory (for example, test-fpga.prj) in the current working directory.

• The console displays the output of the executable to signify a successful execution.

C:\intelFPGA_pro\18.1\hls\examples\QRD>build.bat test-fpga 

i++ --fpc --fp-relaxed -march=Arria10 MGS.cpp QRD_Testbench.cpp

TestbenchHelpers.cpp -o test-fpga.exe

Run test-fpga.exe to execute the test.

Thanks,

Arslan

[MuhammadAr_U_Intel]

Additionally if you wish to see the waveform, add the switch "-ghdl" to compile command.

Refer to HLS compiler user guide for details.

https://www.intel.com/content/www/us/en/programmable/documentation/ewa1457708982563.html#ewa1462823594274

Topic: Debugging during Verification

Hope this helps.

Thanks,

Arslan

[JShel4]

Hi Arslan,

Thanks for the documentation pointers. I cannot say for sure that this all works on CentOS7 (which is what I was trying before) or Ubuntu.

Today I modified my system. I wiped it clean and installed CentOS 6.10. Now, I see that everything is working as expected.

The other change from before is that now, I am using a licensed product (Quartus and ModelSim). Though, I don't suspect that makes any difference.

Thanks for your response. Appreciate you trying to help!

[MuhammadAr_U_Intel]

Glad to know you are able to proceed with CentOS 6.

Officially HLS is supported for REDHAT 6 Linux and Windows 10/7 as of now.

Refer to OS support page.

https://www.intel.com/content/www/us/en/programmable/support/support-resources/download/os-support.html

Thanks,

Arslan