2 to 1 mulltiplexer

Altera_Forum · ‎10-18-2013

Hi all.

I have problem during run VHDL code for 2 to 1 multiplexer. this multiplexer have 8 bit for input and output. while the select bit is only one bit. Here is my coding. However, there is error appear. Do you have solution regarding my problem.

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY part2 IS

PORT( SWX,SWY : IN std_logic_vector (7 downto 0);

s : IN bit;

LEDR : OUT std_logic_vector (7 downto 0));

END part2;

ARCHITECTURE dataflow OF part2 IS

BEGIN

LEDR <= (NOT (s) AND SWX) OR (s AND SWY);

END dataflow;

Altera_Forum · ‎10-18-2013

Try


LEDR <= SWX when (s = '0') else SWY;

Cheers,

Dave

Altera_Forum · ‎10-18-2013

Thank you Dave. It works. No error appear. I want to ask question. Is it possible if I still want used this code "LEDR <= (NOT (s) AND SWX) OR (s AND SWY);" in my architecture? Is there any method to use it. Or is not possible?

Thanks in advance Dave !

Altera_Forum · ‎10-18-2013

--- Quote Start ---

I want to ask question. Is it possible if I still want used this code "LEDR <= (NOT (s) AND SWX) OR (s AND SWY);" in my architecture? Is there any method to use it. Or is not possible?

--- Quote End ---

The above code is asking the synthesis tool to do that for you. What the tool will do is essentially what you have written, but it needs to happen on a per bit basis, eg.,


process(s,SWX,SWY)
begin
   for i in 0 to 7 loop
      LEDR(i) <= (SWX(i) and (not s)) or (SWY(i) and s);
   end loop;
end process;

Note how this code loops over each bit in the 8-bit word.

Cheers,

Dave

Altera_Forum · ‎10-19-2013

Ok. Noted. I already run the code and it works. Thanks dave!