2D array with different number of elements

[Altera_Forum]

Is it possible to have this array in VHDL? 

 [i][j] =  [1][sample1, sample2, sample3] [2][sample1, sample2, sample3, sample4, sample5] [3][sample1, sample2]  It seems like [j] dimension has to be a fixed value.

[Altera_Forum]

--- Quote Start ---   Is it possible to have this array in VHDL?   --- Quote End ---    No.  You could use an array if you changed your format  [i][j] = [1][numvalid, sample1, sample2, sample3, 0 , 0 ] [2][numvalid, sample1, sample2, sample3, sample4, sample5] [3][numvalid, sample1, sample2, 0 , 0 , 0 ]  or you can use a list of lists (or an array of lists).  You'll have to be careful if you're using this for synthesis though.  Cheers, Dave

[Altera_Forum]

i and j have to be a fixed value when you instantiate the signal or variable, as with any language.

[Altera_Forum]

Actually, in Matlab you can have any combination of dimensionality for j. Would Verilog be better at this?

[Altera_Forum]

not really, it all comes down to what is synthesisable, not about which language is better at arrays.