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Valued Contributor III
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2D array with different number of elements

Is it possible to have this array in VHDL? 

 

[i][j] =  

[1][sample1, sample2, sample3] 

[2][sample1, sample2, sample3, sample4, sample5] 

[3][sample1, sample2] 

 

It seems like [j] dimension has to be a fixed value.
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Valued Contributor III
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--- Quote Start ---  

 

Is it possible to have this array in VHDL? 

 

--- Quote End ---  

 

 

No. 

 

You could use an array if you changed your format 

 

[i][j] = 

[1][numvalid, sample1, sample2, sample3, 0 , 0 ] 

[2][numvalid, sample1, sample2, sample3, sample4, sample5] 

[3][numvalid, sample1, sample2, 0 , 0 , 0 ] 

 

or you can use a list of lists (or an array of lists). 

 

You'll have to be careful if you're using this for synthesis though. 

 

Cheers, 

Dave
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Valued Contributor III
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i and j have to be a fixed value when you instantiate the signal or variable, as with any language.

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Valued Contributor III
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Actually, in Matlab you can have any combination of dimensionality for j. Would Verilog be better at this?

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Valued Contributor III
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not really, it all comes down to what is synthesisable, not about which language is better at arrays.

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