Hello friends, how are you?
I'm working on a project and I'd like to add the 6264 (8 bits x 8k blocks) SRAM inside at the FPGA with these VHDL code provided by Cypress.
When compiling, I'm getting these errors:
Warning (10350): VHDL warning at standard.vhd(71): ignored VHDL standard library NOW function, which is not supported for synthesis
Error (10302): VHDL attribute error at cy6264.vhd(180): attribute "event" that is used for multiple bits is not synthesizable
Error (10658): VHDL Operator error at cy6264.vhd(180): failed to evaluate call to operator ""and""
Error (12152): Can't elaborate user hierarchy "cy6264:U24"
I looked for the error about the event attribute and std_logic_vector. I'd like to know how to correct the code to be fully synthesizable. Other minor errors I already solved.
Thanks!
