A little problem how "open and close and locked door"

[Altera_Forum]

library ieee; 

use ieee.std_logic_1164.all; entity uppgift4a_more_2 is port ( -- Insignaler CLOCK, reset_n : IN std_logic; KEY_0, KEY_1 : IN std_logic; -- Utsignaler LEDG_0, LEDG_1,LEDR_0,LEDR_1, led : OUT std_logic); end entity;   architecture rtl of uppgift4a_more_2 is -- Build an enumerated type for the state machine type state_type is (opening_1,closing_2, open, close); -- Register to hold the current state signal state : state_type; begin process (reset_n, CLOCK) begin if reset_n = '0' then state <= opening_1; elsif (rising_edge(CLOCK)) then case state is when closing_2=> if KEY_0 = '1' then state <= close; else state <= closing_2; end if; when close => state <= closing_2; when open => state <= opening_1; when opening_1 =>  if KEY_1 = '1' then state <= open; else state <= opening_1; end if; when others => state <= opening_1; end case; end if; end process; process (state) begin case state is when closing_2=> led <= '1';LEDG_0 <= '0'; LEDG_1 <= '0'; when open => LEDG_0 <= '1'; LEDG_1 <= '0'; led <= '1'; when close => LEDG_1 <= '1'; LEDG_0 <= '0'; led <= '0'; when opening_1 => led <= '0'; LEDG_0 <= '0'; LEDG_1 <= '0'; when others => LED_1 <= '0';LEDR_0 <= '0'; led <= '0'; when opening_1 => led <= '0'; LEDR_0 <= '0'; LEDR_1 <= '0'; when others => LEDG_1 <= '0';LEDR_0 <= '0'; led <= '0'; end case; end case; end process; i vonder what is wrong with this code :unsure: end;

[Altera_Forum]

What kind of error do you have? I only see a double "end case" at the end of the code.

[Altera_Forum]

Error (10500): VHDL syntax error at uppgift4a_Moore_2.vhd(21) near text "open"; expecting an identifier ("open" is a reserved keyword), or a character 

Error (10500): VHDL syntax error at uppgift4a_Moore_2.vhd(42) near text "open"; expecting "(", or an identifier ("open" is a reserved keyword), or unary operator Error (10500): VHDL syntax error at uppgift4a_Moore_2.vhd(47) near text "open"; expecting "(", or an identifier ("open" is a reserved keyword), or unary operator Error (10500): VHDL syntax error at uppgift4a_Moore_2.vhd(62) near text "open"; expecting "(", or an identifier ("open" is a reserved keyword), or unary operator Error (10500): VHDL syntax error at uppgift4a_Moore_2.vhd(81) near text "case"; expecting "process"

[Altera_Forum]

"open" is a reserved key word in VHDL syntax. You should use a different name for that state .

[Altera_Forum]

what name i dont understand i thought (open) was the right so show me ...? :confused:

[Altera_Forum]

As suggested by the Error information given by your compiler: 

   --- Quote Start ---  Error (10500): VHDL syntax error at uppgift4a_Moore_2.vhd(42) near text "open"; expecting "(", or an identifier ("open" is a reserved keyword), or unary operator  --- Quote End ---  "open" is a reserved word in VHDL syntax.  For example, you can change your state_type definition to:  type state_type is (opening_1,closing_2, opened, close)  You can use any name for this state except "open".  Any tutorial on VHDL will give a list of reserved words in VHDL syntax.  When writing code, you should avoid using any of these reserved words as a name of user-defined object, such as signal, variable, entity, architecture, enumerated data types, etc.

[Altera_Forum]

I have done that,now i have a error Error (10500): VHDL syntax error at uppgift4a_Moore_2.vhd(13) near text ":"; expecting an identifier 

     this is the text>LEDG_0, LEDG_1,LEDR_0,LEDR_1,: OUT std_logic);

[Altera_Forum]

now you have an extra comma before ": OUT". Type: 

 LEDG_0, LEDG_1,LEDR_0,LEDR_1 : OUT std_logic);  But in the original code you have:  LEDG_0, LEDG_1,LEDR_0,LEDR_1,led : OUT std_logic);  ¿Do you delete "led"?

[Altera_Forum]

led should be

[Altera_Forum]

This is the new one i vonder if its right or wrong and someone can help me do it right "tanks:rolleyes:" 

 library ieee; use ieee.std_logic_1164.all; entity uppgift4a_more_2 is port ( -- Insignaler CLOCK, reset_n : IN std_logic; KEY_0, KEY_1,KEY_2,KEY_3: IN std_logic; -- Utsignaler LEDG_0, LEDG_1,LEDR_0,LEDR_1,led : OUT std_logic); end entity;  architecture rtl of uppgift4a_more_2 is -- Build an enumerated type for the state machine type state_type is (opening_1,closing_2, opened, close,locked,locking_2,unlocked,unlocking_3); -- Register to hold the current state signal state : state_type; begin process (reset_n, CLOCK) begin if reset_n = '0' then state <= opening_1; elsif (rising_edge(CLOCK)) then  case state is    when closing_2=>    if KEY_0 = '1' then    state <= close;  else  state <= closing_2;  end if;    when close =>  state <= closing_2;  when locking_2=>     if KEY_2 = '1' then    state <= locked;  else   state<= locking_2    when unlocking_3=>  if KEY_3 ='0'  then   state <=unlocked  else  state<=unlocking_3      when opening_1 =>   if KEY_1 = '1' then  state <= opened;   else  state <= opening_1; end if; when others =>  state <= opening_1; end case; end if; end process; process (state) begin case state is when closing_2=> led <= '1';LEDG_0 <= '0'; LEDG_1 <= '0'; when opened => LEDG_0 <= '1'; LEDG_1 <= '0'; led <= '1'; when close => LEDG_1 <= '1'; LEDG_0 <= '0'; led <= '0'; when opening_1 => led <= '0'; LEDG_0 <= '0'; LEDG_1 <= '0'; when others => LED_1 <= '0';LEDR_0 <= '0'; led <= '0'; when opening_1 => led <= '0'; LEDR_0 <= '0'; LEDR_1 <= '0';   LEDG_1 <= '0';LEDR_0 <= '0'; led <= '0'; when others => end case; end process; end;

[Altera_Forum]

Syntax errors are something you should really be fixing yourself. Also, testing it is also something you should be doing yourself, not asking others to do it for you.