AHDL Simulation

[Annu]

How do we simulate an AHDL file in Text format using VHDL testbench using Quartus ii tool

[KennyTan_Altera]

sorry for the late reply, what you can do is convert the file to the HDL files.

In Quartus prime std, click file -> create update -> create HDL file from current files.

Please take note that AHDL is already deprecated from the support.

[KennyTan_Altera]

do you have more question? If no, we shall close this thread.

[KennyTan_Altera]

As we do not receive any response from you on the previous reply that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.