AHDL to VHDL

[Altera_Forum]

Hi All,  

 I have one project and all design files are written in AHDL and 10 yrs old. I want to convert them to VHDL so that I can simulate them. I tried Xilinx XPORT utility but lot of errors.    Appreciate for your kind help.    -Vijay

[Altera_Forum]

Synthesize them in Quartus and write out a VHDL/Verilog simulation file(Assignments -> Settings -> EDA). By default it runs after fit, but I think you can run it after synthesis only. The added benefit is you're actually simulating what Quartus synthesizes it too, not what something like XPORT sees. The downside is that you loose a lot of internal combinatorial names that get absorbed into LUTs, plus it's an additional step each time. (Although I'm guessing it runs pretty quick...)

[Altera_Forum]

--- Quote Start ---   I have one project and all design files are written in AHDL and 10 yrs old. I want to convert them to VHDL so that I can simulate them. I tried Xilinx XPORT utility but lot of errors.     --- Quote End ---    As Rysc points out, your best option is to synthesize to .vho output and use that for simulation.  This is also the best route to take if you want to port the AHDL to VHDL. If you do have to port the code to VHDL, then I would recommend first creating a testbench that tests the complete functionality of the .vho version of the AHDL file. You can then run that same testbench on your ported VHDL code to confirm it retains the functionality of the original AHDL code.  Cheers, Dave