Creating generated clocks in timequest

[Altera_Forum]

Hi, 

 I am having some trouble getting to grips with constraining generated clocks in timequest.  My design uses a couple of outputs from a counter to drive clock inputs on external devices on my board. The clock input of the counter is driven by an external PLL connected to one of the dedicated clock inputs on the device (3C10).  I do not have an on chip PLL available to generate the required exernal clocks. Moving to a larger device may be possible as a last resort but I would prefer not to.  My attempts to constrain the clocks using the create_generated_clock command fail.  Warning (332060): Node: global_signals:inst|pll_ctr:inst3|lpm_counter:LPM_COUNTER_component|cntr_c8i:auto_generated|counter_reg_bit was determined to be a clock but was found without an associated clock assignment. Warning (332088): No paths exist between clock target "bus_mclk" of clock "mclk" and its clock source. Assuming zero source clock latency.   Is there an application note that explains how to constrain clocks generated by counters?  In othere forum posts I have seen reference to "Timing Analysis of Internally Generated Clocks in Timequest v2.0.doc" but this document seems to be unavailable now.  Thanks bb.

[Altera_Forum]

Anytime a register's output drives the clock port of other registers, i.e. a ripple clock, then a create_generated_clock must be applied to the register. I'm not completely sure why, but assume that since a register will always change the frequency, just passing the base clock through is incorrect. In your case, probably something like: 

create_generated_clock -name "ripple_clk_2mhz" -source [get_ports sys_clk] -divide_by 16 [get_keepers {global_signals:inst|pll_ctr:inst3|lpm_counter:LPM_COUNTER_component|cntr_c8i:auto_generated|counter_reg_bit[0]} Obviously the name, source and divide_by need to be changed. Note that the -source is always a physical node in the design, not a clock that was created in your .sdc. (TimeQuest finds the clock on that physical node and uses it through). If you have ripple clocks feeding ripple clocks, then you need a generated clock at each stage. Hope that helps.

[Altera_Forum]

Hi Rysc, 

 thanks, that helps.  The counters that I am using are created using the megawizard generated component LPM_COUNTER. Do you know if these are ripple counters or not?   Using the locate in RTL view, the clocks to each of the registers are are all fed from a common clock, with logic in the feedback path.  I am using this to create the generated clock:  create_generated_clock -name mclk -source -divide_by 2 |q}] create_generated_clock -name bclk -source -divide_by 8 |q}]   pll_clk is the name of the physical clock pin of the device. Is this correct, or should I specify the clock node of the register?  Thanks bb

[Altera_Forum]

Looks correct. LPM_COUNTER should be just a regular counter built with carry-chains. (Each output, if used as a clock, is a ripple clock, but they don't ripple into the next bits clock port, i.e. they're all driven by pll_clk) 

Also note that if you drive this clock off chip and want to relate data to it, you need another generated clock, i.e.: create_generated_clock -name "mclk_out" -source [get_pins {inst|pll_counter|LPM_COUNTER_component|auto_generated|counter_reg_bit[0]|q}] [get_ports mclk_out]  That tells how the clock leaves the chip. You could then use mclk_out as the -clock option for a data output's set_output_delay constraint. I'm not sure what you're doing, just mentioning it as an option.

[Altera_Forum]

Rysc, thanks. 

 Your suggestion of another generated clock to drive off chip is exactly what I will be doing, thanks for the tip.   Cheers bb