I have been trying to simulate a Qsys-generated test bench, but I have been getting an error I cannot fix. I have been using Quartus 11.0 and Modelsim Altera edition 6.6d. The design targets a Cyclone IV GX.
I have a qsys-based design that implements a PCIe core, some clocks, and a custom module. It compiles fine. I have the Qsys generate tab set to create a Verilog simulation module, a standard test bench, and a verilog test bench simulation model.
I run ModelSim, change to the <design_path>/testbench directory, and run the msim_setup.tcl script. I run "com", and it succeeds. "dev_com" does not seem to do anything. Running "ld" compiles a lot of files successfully, but fails running:
vsim -l work -l altera_ver -l lpm_ver -l sgate_ver -l altera_mf_ver -l altera_lnsim_ver -l cycloneiv_hssi_ver -l cycloneiv_pcie_hip_ver -l cycloneiv_ver -t ps qsys_top The error message is:
** error: (vsim-3170) could not find 'c:\work\pcie_test_qsys\qsys_top\testbench\work.qsys_top'. There is a qsys_top.v file in the synthesis folder and in the simulation folder, but not in the testbench folder. I tried running ModelSim from the simulation folder, but there are no test benches to drive the entity. What do I need to do to get the test bench running?
