ARRIA 10 soc development kit schematic

[srinivasan]

can anyone send the proper schematic for  arria 10 soc development kit?

[sstrell]

This one?

https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/arria-10-soc-development-kit.html

All the files you need are there.

[srinivasan]

Hi strel,

  I got the schematic...But

  In the schematic , DDR4 signals pin connection was different from quartus EMIF IP pin signals(pin planner)...

can u share the DDR4 pin connections?

[AR_A_Intel]

Hi Srinivasan

May we know what is the pin deferent? And source you refer to? Provide the link to it. 

[srinivasan]

Hi,

 I got it..thanks for your reply...

Error(14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 DQ_GRP(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error(175020): The Fitter cannot place logic DQ_GRP that is part of Generic Component ed_synth_emif_0 in region (148, 33) to (148, 44), to which it is constrained, because there are no valid locations in the region for logic of this type.
Info(14596): Information about the failing component(s):
Info(175028): The DQ_GRP name(s): emif_0|emif_0|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[1].lane_inst_DQ_GRP_1
Error(16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:
Error(175005): Could not find a location with: DQ_X9 (1 location affected)
Info(175029): DQ_GRP containing AT5
Info(175015): The I/O pad emif_0_mem_mem_dq[8] is constrained to the location PIN_AK8 due to: User Location Constraints (PIN_AK8)
Info(14709): The constrained I/O pad is contained within a pin, which is contained within this DQ_GRP

can you give solution for above error?

[AR_A_Intel]

Hi

Thanks for update. The error message is regarding EMIF design fitter error related and it is out of my expertise. I’m only familiar with board basic usage enquiry. Please be inform that we have different engineers to handle different field of specialty. If you need help on EMIF design fitter error debug, I suggest you to open/submit a new request for Intel EMIF support team to take a look into it.

Please accept my apologies for not being able to assist you fully as this is out of my expertise.

[AR_A_Intel]

We have not heard from you and I hope that my last note clears up this matter. If you don’t have any further question, I will now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.