Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Maximum Input Clock for FIFO

m_kumar
New Contributor I
881 Views

Hi 

Iam using max10  fpga , having dought regarding to fifo memory block, what is the maximum input clock can be given to fifo ip. 

In my project iam using fifo dual clock mode.

write clock = 240 Mhz,

read clock = 60 Mhz,

I studied device data sheet not find any information for the dought.

Thanks in Advance.

 

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Ash_R_Intel
Employee
866 Views

HI Manoj,


The FIFO IP uses the M9K memory component as basic block along with some logic elements. The achievable frequency is determined by overall design in the FPGA.

The datasheet provide details of M9K block used in FIFO mode for a fixed configuration. This can be considered as the basis for your estimation.

However, the actual frequency achieved can only be found out from the final Timing Analyzer report.


Regards,

Ashlesha


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m_kumar
New Contributor I
859 Views

Hi Ashlesha,

I found this details in datasheet here they mentioned that we can give input clock upto 300 MHz.

fifo.PNG

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Ash_R_Intel
Employee
841 Views

Hi,

Hope you have got answer to what you are looking for. Is it ok to close this case?


Regards.


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m_kumar
New Contributor I
838 Views

Hi ,

I have changed my design and reduced input clock to 80Mhz, now i am moving with the project. Anyway thanks for the information.

Regards

Manoj

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