Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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About TimeQuest Unconstrained Paths

Altera_Forum
Honored Contributor II
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https://www.alteraforum.com/forum/attachment.php?attachmentid=8489 https://www.alteraforum.com/forum/attachment.php?attachmentid=8490  

I want to synchronize the clock"in"to the clock"clk",and get the clock trigger the data. 

But after compiled ,the Report give the hint as shown in figure . "inst" is not a base clock, how to deal with it?
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Altera_Forum
Honored Contributor II
478 Views

 

--- Quote Start ---  

https://www.alteraforum.com/forum/attachment.php?attachmentid=8489 https://www.alteraforum.com/forum/attachment.php?attachmentid=8490  

I want to synchronize the clock"in"to the clock"clk",and get the clock trigger the data. 

But after compiled ,the Report give the hint as shown in figure . "inst" is not a base clock, how to deal with it? 

--- Quote End ---  

 

 

you must have connected inst to the clock port of a register either directly or by inference.
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Altera_Forum
Honored Contributor II
478 Views

sorry,I can't understand what's your meaning . 

can you tell me details ? in figure, "in" is a 10MHz clock , "clk" is a 320MHz clock, I want to get a synchronize clk to trigger the data, so... 

this program is normal in Classic Timing Analyzer, but in TimeQuest , it gives the warning. 

why?
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Altera_Forum
Honored Contributor II
478 Views

 

--- Quote Start ---  

sorry,I can't understand what's your meaning . 

can you tell me details ? in figure, "in" is a 10MHz clock , "clk" is a 320MHz clock, I want to get a synchronize clk to trigger the data, so... 

this program is normal in Classic Timing Analyzer, but in TimeQuest , it gives the warning. 

why? 

--- Quote End ---  

 

 

your picture includes a node called "inst" but you haven't told us anything about it.
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