About "delayed addition" in fitter report

[Yamada1]

I am designing a design that takes in ADC data and performs signal processing, but due to the mismatch in PN placement on the ADC side and FPGA side and the need to make equal length wiring on the board, some signals I'm trying to turn it over and take it in. (For example, data(9) is reversed in data(0) to data(11))

At this time, the signal that is not inverted after fitting is listed in "Estimated Delay Added for Hold Timing Details". (Numbers are also listed in "Delay Added in ns")

It would be helpful if you could teach me what it means.

Also, would this affect timing analysis?

I'm sorry to trouble you, but it would be helpful if you could teach me.

that's all

[sstrell · Accepted solution]

By default, the Fitter intentionally adds additional routing delay where needed to help meet hold timing requirements.  You can disable this globally in the optimization settings (I forget where and don't have Quartus open at the moment) or I think there is an assignment you can use in the Assignment Editor to specify where you want this done (or not).

[Yamada1]

Thank you for answering.

Thank you for your detailed explanation.

It was very helpful.

[RichardTanSY_Intel]

Thank you for acknowledge the solution provided. 

To add-on, the setting that Strell mentioned is called "Optimize Hold Timing". (Project>Setting> Compiler Setting > Advanced Fitter Setting)

As your question has been addressed, I now transition this thread to community support. 

Thank you.

Best Regards,

Richard Tan