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## About the concept of "set_output_delay constraint"

Beginner
781 Views

It would be helpful if you could teach me about the concept of "set_output_delay constraint".

I read the materials provided by Intel and the materials posted on the web, but there were some parts that I could not understand, so it would be helpful if you could teach me the following points.

1) The -min option is the value referred to in hold timing analysis, which is the minimum value of the delay time in the design.

Is it correct to recognize that it is a value that indicates whether or not

2) If the understanding of 1) is correct, is it correct to understand that the set value of the -min option may be larger depending on the setup/hold time of the connected device?

3) There may be formulas posted on the web for calculating setting values. The formula for calculating the minimum data delay time in the common clock method is

Tdata_min - Th + Tclk2_min - Tclk1_max

Tdata: Delay time of data on PCB

Tclk1: clock arrival time to receiving device

Tclk2: clock arrival time to target FPGA

Th: Hold time of the receiving device

It is Assuming that the above formula is correct, is the following interpretation correct?

"If the result is negative, it indicates that the delay time on the PCB cannot satisfy the hold time of the receiving device, and we need to add delay in the FPGA. If the result is positive, it means the delay time on the PCB." satisfies the hold time of the receiving device and does not require any additional delay in the FPGA."

Assuming that this interpretation is correct, if the result of the above formula is negative, its absolute value will be set as the setting value of the -min option, and if it is positive, the setting of the min option is not necessary.

Is it correct?

Sorry for the long and elementary question, but it would be helpful if you could teach me.

1 Solution
Employee
633 Views

When you mention 2), I believe this is the question you are referring to:

"2) Depending on the values of tsu_ext and th_ext, the result of the formula may be "output delay max < output delay min", but does that mean there is no problem?"

Yes, it is possible for the setting value of set_output_delay -min to be larger than the setting value of set_output_delay -max depending on the setup/hold time of the downstream device/ external circuit.

If the downstream device has a shorter setup time requirement, then the set_output_delay -min value can be larger than the set_output_delay -max value. This is because a larger delay would be needed to ensure that the output signal meets the shorter setup time requirement.

Conversely, if the downstream device has a shorter hold time requirement, then the set_output_delay -max value can be larger than the set_output_delay -min value. This is because a smaller delay would be needed to ensure that the output signal meets the shorter hold time requirement.

In summary, the setting values of set_output_delay -min and -max can vary depending on the timing requirements of the downstream device. It is important to carefully analyze the timing requirements of the entire system to determine appropriate delay values for each constraint.

Hope that helps to clarify. : )

Best Regards,

Richard Tan

9 Replies
Honored Contributor III
761 Views

1) Not quite understanding what you are saying here, but set_output_delay -min lets you specify the minimum external delay for data to reach the downstream device and remain stable long enough to meet that device's hold timing requirement.  Based on this value, the compiler adjusts tco of the output to meet the requirement.

2) "Larger" than what?  But yes it is based on the external path delay and the th of the downstream device to calculate the hold required time for that device.

3) Your equation seems off.  The clock skew calculation doesn't look correct.  (EDIT: oh, your definitions of clk1 and clk2 are swapped from what I have below so they are the same.)  Should be:

output delay min   = Data trace (min) - Board clock skew (max) – Th

= (Tdata_PCB(min) + TCL (delay due to capacitive loading if you want to include it)) - (Tclk2(max) – Tclk1ext(min) ) - Th

As for your interpretation, it seems correct but you should always have set_output_delay -min in your .sdc no matter the value to ensure the path does not appear as unconstrained.

Beginner
749 Views

Thank you for answering.

"1)" was intended to ask about the concept of set_output_delay -max, but the sentence was cut off in the middle. very sorry.

It would be helpful if you could teach set_output_delay -max in the same way.

As for "2)", I asked whether the setting value of set_output_delay -min may be larger than the setting value of set_output_delay -max depending on the setup/hold time of the downstream device, but "1)" It was a meaningless question because it was a description of the premise that there was a description of set_output_delay -max in . very sorry.

Thank you for showing the calculation formula.

I'm checking because the machine translation doesn't seem to work well, but the formula you provided is

Tclk2(max) : Clock arrival time to downstream device

Tclk1ext(min): clock arrival time to target FPGA

Is that all right?

Sorry for the inconvenience, but thank you in advance.

Community Manager
735 Views
Beginner
719 Views

Thank you for answering.

I confirmed it, but the calculation formula was the same as the one I confirmed, so I recognized that there was no problem.

I would appreciate it if you could let me know if there is anything that bothered me about the description of the material.

1) Timing Analyzer automatically determines the start clock because all the clocks that start the output data are defined.

If so, does it mean that correct analysis results can be obtained if the startup clock is specified even if the virtual clock is not specified?

2) Depending on the values of tsu_ext and th_ext, the result of the formula may be "output delay max < output delay min", but does that mean there is no problem?

Sorry for the inconvenience, but thank you in advance.

Community Manager
685 Views

If so, does it mean that correct analysis results can be obtained if the startup clock is specified even if the virtual clock is not specified?

- No, even if the startup clock is mentioned, accurate analysis findings cannot be acquired if the virtual clock is not stated. The virtual clock, which is usually the quickest clock in the system, serves as the reference clock for timing analysis.

The Timing Analyzer cannot precisely determine the timing routes and violations in the architecture without knowing the virtual clock. To carry out a precise timing analysis, it is crucial to specify both the starting clock and virtual clock.

Beginner
667 Views

Thank you for answering.

Thank you for your detailed explanation.

If possible, it would be helpful if you could also provide information on 2) of the above question.

Sorry for the inconvenience, but thank you in advance.

Employee
634 Views

When you mention 2), I believe this is the question you are referring to:

"2) Depending on the values of tsu_ext and th_ext, the result of the formula may be "output delay max < output delay min", but does that mean there is no problem?"

Yes, it is possible for the setting value of set_output_delay -min to be larger than the setting value of set_output_delay -max depending on the setup/hold time of the downstream device/ external circuit.

If the downstream device has a shorter setup time requirement, then the set_output_delay -min value can be larger than the set_output_delay -max value. This is because a larger delay would be needed to ensure that the output signal meets the shorter setup time requirement.

Conversely, if the downstream device has a shorter hold time requirement, then the set_output_delay -max value can be larger than the set_output_delay -min value. This is because a smaller delay would be needed to ensure that the output signal meets the shorter hold time requirement.

In summary, the setting values of set_output_delay -min and -max can vary depending on the timing requirements of the downstream device. It is important to carefully analyze the timing requirements of the entire system to determine appropriate delay values for each constraint.

Hope that helps to clarify. : )

Best Regards,

Richard Tan

Beginner
626 Views

Thank you for answering.

I was able to solve my doubts. thank you very much.

Employee
624 Views

You're welcome.

I am happy to help.

Best Regards,

Richard Tan