Avalon MM Master BFM

[Aswinkrishnan]

I have followed the ug_avalon verification example test program and modified it with a custom slave. I have removed the slave thread.

In the test program, the command is written to a randomly generated address with a slave id.

Can I change that and specifically write to a particular address in the slave register? Is there a specific format to include an address? It's returning an error when I include the hex address format.

[sstrell]

Can you show the hardware setup in Platform Designer and the code?

[RichardTanSY_Intel]

Could you help to share the test program's code?

We have a BFM simulation example in the link below. Not sure if it will helps you in anyway.

https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-examples/quartus/exm-hps-axi-bfm.html

Best Regards,

Richard Tan

[Aswinkrishnan]

In this test program, I wanted to write a data in to a specific register in the slave and the way it is to be done is by changing the cmd.address

I had modified the test program by removing slave thread.

Now I need the master to write data into the slave in multiple address locations. How can I do that?

[Aswinkrishnan]

Hi

In this test program written in VHDL, instead of generating random aligned address, how can I modify such that the master first send a command to an address and then send another data to another address.

For example

write command data to location between 32'hc0 to 32'hce. and then send another data to a location say 32'h9f.

My slave consists of several components such as a pulse sample interface, laser drive, sequencer etc.

I need to execute each in an order. Can I do that?

Regards

Aswin

[RichardTanSY_Intel]

You can checkout the example test program here:

There are 3 components connected to BFM master: PIO Control, PIO Status, On-chip RAM

In which the BFM perform read/write to these components in order.

Best Regards,

Richard Tan

[Aswinkrishnan]

Thank you for this example. I tried changing in the test program.sv but only could manage one component at a time, not successively.

I shared that as a VHD file but I am currently working in verilog. I will look in to your example and understand, in the meantime, if there is an example written in verilog, it would be helpful.

Regards

Aswin

[RichardTanSY_Intel]

Here's one in System Verilog format.

[Aswinkrishnan]

Thank you for your message. Now this example is for multiple slave devices and single master. Should I use this with the test_program.sv?

Moreover, In my case, there is one slave component which includes a few sub components. Therefore, What I need to do is writing into register across the same slave component. 
For example, write data into 'hc0 to 'hce and write to 'h9f and so on. So will the above example helps me in that case?

I was trying to modify test_program.sv. I have a few questions

1.  Can I replace the structure Command with an array of Command struct. Hence, each location consist of a particular address and iterate through it?

example snippet below:

typedef struct
{
Transaction trans;
Burstcount burstcount;
logic [ADDR_W-1: 0] addr;
logic [DATA_W-1:0] data [MAX_BURST-1:0];
logic [NUM_SYMBOLS-1:0] byteenable [MAX_BURST-1:0];
bit [31:0] cmd_delay;
bit [31:0] data_idles [MAX_BURST-1:0];
} Command;

can I change this in to an array of struct like in C?  ( }Command[2]; )

While doing that, compiler returning the error that it failed to create a packed array from unpacked array.

[RichardTanSY_Intel]

The testbench example is just a guidance and you may need to modify it accordingly to your need. If you want to use any Avalon-MM transactions, i.e., writesingle, read-single, write-burst, and read-burst, please take note that the Avalon-MM read/write single/burst transactions have all been configured for minimum transaction time, i.e., no initial latency, and no idle time between transactions. This setting may not reflect the real Avalon-MM master you use in your particular hardware design, so you may want to adjust these transactions according to your needs. If however your Avalon-MM slaves have been verified with complete code coverage, then these minimum transactions should be acceptable.

And I think it should be possible to write a testbench to specific address as shown in the example provided previously.

Typedef should be supported in System Verilog. You might have do dive deep into what's goes wrong. Check the Questa SIM User Manual.

[Aswinkrishnan]

Yeah I will look in to that. I just wanted your opinion on the error using array of structures in system verilog.

Moreover, this test bench file must be used as part of test_program.sv file? There was a tb file that was provided with it and only needed to replace that with?

[RichardTanSY_Intel]

Sorry for the late reply. I was on leave for a few days.

Yes, you can add/modify the testbench example into the test_program.sv that you have initially.

I think I haven't attach the package here as the Altera Avalon-MM Master BFM procedures used in the testbench (qsys_system_tb.vhd) were extracted into a package and the testbench was updated to use the procedures in that package.

Compile both the new package and modified testbench, to use the BFM.

[RichardTanSY_Intel]

Do you need further help in regards to this case?

[RichardTanSY_Intel]

As we do not receive any response from you on the previous question/reply/answer that we have provided. I now transition this thread to community support. 

Best Regards,

Richard Tan