About the minimum value constraint (-min option) of "set output delay"

[Yamada1]

I use "set output delay" when constraining the timing between the FPGA and the subsequent device, but it would be helpful if you could tell me the following points about the minimum value constraint (-min option).

1) On the web, etc., the formula for calculating the setting value is

(Delay on board) - (Clock skew on board) - (Hold time of subsequent device) Is this correct? It would be helpful if you could present any documents that can be confirmed.

2) Assuming that the above formula is correct, if the calculated value is a positive value, the delay on the board alone will satisfy the hold time of the subsequent device. Is it correct to understand that the hold time of the subsequent device cannot be satisfied?

3) If the recognition in 2) is correct, a negative value setting exists, but none of the samples had a negative value set. I think my understanding is probably wrong, but I would appreciate it if you could enlighten me.

Sorry for the long post. Also, please note that the text may be difficult to understand due to machine translation.

[sstrell]

For all of this, check out this training: https://cdrdv2.intel.com/v1/dl/getContent/652837?explicitVersion=true

1) Yes, this is correct.   Discussed in the training and the Timing Analyzer user guide found here: https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-software/user-guides.html

2) The calculated value here is just for the constraint to basically tell the Fitter how early the signal can be launched from the FPGA and still remain active and stable long enough to meet hold timing.  Are you asking about the actual slack on the path to the external (downstream) device?  If the slack is positive, then it meets hold timing.  If it's negative, it fails.  The value you enter into the constraint is not slack.

3) Again, the value here is not slack.  There's no reason why the output delay min value can't be negative but you still get positive slack for the path.

[Yamada1]

Thank you for answering.

　Delay on board=1ns

　Clock skew on board = -1ns

　Hold time of subsequent device=3ns

In the above conditions, the setting value of "set output delay -min" can be calculated as 1-(-1)-3=-1ns. If this is set as a setting value of "set output delay -clock[clk] -min -1 [get ports DATA]", then "DATA delay from the clk edge must be 1 ns or more to satisfy the hold time". Is it correct to understand that the Fitter is notified of this?

I'm sorry to trouble you, but it would be helpful if you could teach me.

[Nurina · Accepted solution]

Hello,

You can find set_output_delay documentation here: https://www.intel.com/content/www/us/en/docs/programmable/683243/23-1/output-constraints-set-output-delay.html

Yes, fitter is notified of the setup and hold timing requirements from the set_output_delay. So fitter will do its best to meet this requirement during place & route.

Regards,

Nurina

[Yamada1]

Thank you for answering.

Also, thank you for introducing the materials.

It was very helpful.

[Nurina]

Hi,

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Feel free to open a new thread or login to ‘ https://supporttickets.intel.com ’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

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Best regards,

Nurina W.

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