When I synthesize one project with DDR4 module, I face one strange probelm:
I constrained DDR4 refclk in my sdc file and set -exclusive for this DDR4 refclk, but from the sta report, It presents the timing violation which occured at the DDR4 refclk domain, but from the timing violation path, I found that these paths belongs to the DDR4_emif_o_refclk(DDR4 controller outputs) domain and there is no rationship with DDR4 refclk. So I don't know what's wrong? Of course, now I don't assignments pins for all I/O pins in top-level, but I don't think this effects the timing analysis. So, Could someone will help me or give me some advice about this problem?
What device are you using? Is this a hardened EMIF or soft? Yes, the placement of pins would have an effect on timing analysis. Make sure all of your constraints, including I/O pin locations, are created to get an accurate analysis.
Device : arria 10 , 10ax115s2f45i1sg
EMIF: hard controller & PHY
Pin placement: no placement constrains for all EMIF interfaces (make quartus II assignment automatically)
And I found that I make one ddr refclk constrains in my .sdc file though there is one ddr refclk constrains in the .sdc file which generated with EMIF IP generation, and there is timing violation; And if I don't make this clock constrains in my .sdc file, there is no timing violation apperence. I think this constrain conflicts with the content of the clock constraints in EMIF.