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I am currently using a Cyclone 10 LP device with an EPCS16 program memory in Quartus Prime 17.1 and Platform Designer.
Is it possible to use the dedicated AS Pins as regular I/O together with the Altera Serial Flash Controller IP in this device? My intention is to connect another SPI device on the very same bus in the application. This IP uses the dedicated AS Pins and does not provide the signals on the topmodule. Maybe there is another IP that can be used for this purpose? This was possible earlier when using the EPCS Serial Flash Controller IP on Cyclone IV E and Quartus II 12.0. But this IP cannot be used in Quartus Prime 17.1. I appreciate any input on this topic.Link Copied
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Hi,
--- Quote Start --- I am currently using a Cyclone 10 LP device with an EPCS16 program memory in Quartus Prime 17.1 and Platform Designer. Is it possible to use the dedicated AS Pins as regular I/O together with the Altera Serial Flash Controller IP in this device? --- Quote End --- Yes, 1.In all Intel device families except Cyclone III, Cyclone IV, and Intel Cyclone 10 LP the EPCS serial flash controller core does not create any I/O ports on the top-level Platform Designer system module. If the EPCS device and the FPGA are wired together on a board for configuration using the EPCS device (in other words, active serial configuration mode), no further connection is necessary between the EPCS serial flash controller core and the EPCS device. 2.When you compile the Platform Designer system in the Intel Quartus Prime software, the EPCS serial flash controller core signals are routed automatically to the device pins for the EPCS device. 3.You, however, have the option not to use the dedicated pins on the FPGA (active serial configuration mode) by turning off the respective parameters in the MegaWizard interface. When this option is turned off or when the target device is a Cyclone III, Cyclone IV device, or Intel Cyclone 10 LP you have the flexibility to connect the output pins, which are exported to the top-level design, to any EPCS devices by setting Dual-purpose pins. For more information refer to section 14.2 https://www.altera.com/en_us/pdfs/literature/ug/ug_embedded_ip.pdf Let me know if this has helped resolve the issue you are facing or if you need any further assistance. Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)- Mark as New
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Hello,
thank you for your answer. As i mentioned in my post, I cannot use the EPCS Flash Controller IP in the Platform Designer for Cyclone 10 LP devices. The IP is marked as Legacy and i get the error message "Component xyz does not support selected device family Cyclone 10 LP". Even though the User Guide, as you mentioned, explicitly lists the Cyclone 10 LP device for this IP, I get this error message. I wanted to use the "Altera Serial Flash Controller" instead, but this IP does not provide the pins on the topmodule. Is there a IP that I am missing? Can you reproduce this behaviour on Quartus Prime 17.1.1.593? Best regards, Christopher- Mark as New
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Hi,
--- Quote Start --- Hello, thank you for your answer. As i mentioned in my post, I cannot use the EPCS Flash Controller IP in the Platform Designer for Cyclone 10 LP devices. The IP is marked as Legacy and i get the error message "Component xyz does not support selected device family Cyclone 10 LP". Even though the User Guide, as you mentioned, explicitly lists the Cyclone 10 LP device for this IP, I get this error message. I wanted to use the "Altera Serial Flash Controller" instead, but this IP does not provide the pins on the topmodule. Is there a IP that I am missing? Can you reproduce this behaviour on Quartus Prime 17.1.1.593? Best regards, Christopher --- Quote End --- I think you are using a serial flash controller IP. You should use legacy EPCS/EPCQX1 flash controller IP. Let me know if this has helped resolve the issue you are facing or if you need any further assistance. Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation) https://alteraforum.com/forum/attachment.php?attachmentid=14935&stc=1- Mark as New
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Hello,
I wanted to use the Legacy EPCS/EPCQx1 Flash Controller, but I get the error message "Component epcs_flash_controller_0 does not support selected device family Cyclone 10 LP", see the attached screenshot. That is the reason why I tried the Serial Flash Controller IP, which only uses the dedicated pins. Is there another IP that provides the same functionality as the Legacy EPCS/EPCQx1 Flash Controller, but is supported by the Cyclone 10 LP? Can you reproduce this behaviour on Quartus Prime 17.1.1.593? Best regards Christopher- Mark as New
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Hi Christopher,
Apologies, Yes, got the same error message for a flash controller. we will come back on this issue as soon possible. Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)- Mark as New
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Hi,
cyclone 10 lp does not support legacy epcs/epcqx1 flash controller ip. the respective documents will be updated. Consider either using ASMI Parallel IP or ASMI Parallel II IP which has similar feature: https://www.altera.com/en_us/pdfs/literature/ug/ug_altasmi_parallel.pdf https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug-asmi2.pdf Let me know if this has helped resolve the issue you are facing or if you need any further assistance. Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)- Mark as New
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Hi Christopher,
I am Joseph from Intel Customer Support team. Currently, we are acknowledging this issue as documentation error. Anand as our first level agent that support this case has done the replication testing and get the same result at our end. Did confirm with Intel internal team that legacy EPCS/EPCQX1 flash controller IP isn't supported on Cyclone 10. Therefore, its going to be a correctional on the documentation that capture this incorrectly. The fixing date is tentative at the time being and we will notify you once we have commitment from owning division. Your Truly, Joseph Cheah Intel Customer Support - Engineering Sales Marketing Group (This message was posted on behalf of Intel Corporation)- Mark as New
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Hi Christopher,
The documentation fix on version 18.0 is confirmed. The release date will be somewhere around Q2 2018 time frame. Therefore, I will closed this case as of now since it just a documentation error.
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