Analysis & Synthesis Error(13224): Verilog HDL or VHDL error "..:" index -8 is out of range [15:0]..

[Ranesh]

Hi,

I have following error while Analysis & Synthesis using Qyartus 21.2 and 22.2:

Error(13224): Verilog HDL or VHDL error at vector_capture.sv(143): index -8 is out of range [15:0] for 's_in_data'

I have added my project (vector_capture_21_2). The project can be found in vector_capture_21_2\quartus_proj and source files can be found in vector_capture_21_2\src

According to my code and parameter assignments, the index cannot be -8, but I am not clear how the tool see -8 as an index.

Can someone help me to overcome this issue?

Thank you,

Ranesh

[Ranesh]

Hi Sheng and Frank

Have you got any answer for this issue?

Regards,

Ranesh

[ShengN_Intel]

Hi Ranesh,

Based on internal engineering team, this is expected behavior but not bug:

Below is the expert explanation on the second example (s_outbytecount) and first example (s_in_empty):

s_output_data[d] <= s_in_data[((W_MODULE_DATA - ((d - s_outbytecount) * 8))- 1) -: 8]; //vector_capture_v2.sv, line number 151

In this case, array index uses logic type variable "s_outbytecount", for which synthesis generates a circuit which ensures no out of bound error happens.

In original use case, when local param is used in the index operation, they are replaced with actual values in compile time, so all possible indices get generated which cause out of bound error during loop unrolling.

e.g.

s_in_data[((W_MODULE_DATA - ((c - c_IN_DESC_BYTE_CNT) * 8)) - 1) -: 8]

Here, c is running from 16 to 31. During loop unrolling, index value is generated for all values of c which causes out of range error.

Thanks,

Sheng

[FvM]

Hi Ranesh,

as written above, dependency of variable part select on s_in_empty causes the problems. You can easily check by commenting out s_in_empty. I don't attempt to decide if System Verilog requires an indirectly dependant part select to be calculated correctly by Quartus compiler or not. 

In any case, the problem can be easily bypassed by a direct comparison of the actual part select index against a constant limit.

for (int c = c_IN_DESC_BYTE_CNT; c < c_OUT_DATA_BYTE_CNT; c++)
  begin
    int idx = W_MODULE_DATA - ((c - c_IN_DESC_BYTE_CNT) * 8);
    if ((c < (c_IN_DESC_BYTE_CNT + (c_IN_DATA_BYTE_CNT - s_in_empty))) && idx >= 8 )
      s_output_data[c] <= s_in_data[((W_MODULE_DATA - ((c - c_IN_DESC_BYTE_CNT) * 8)) - 1) -: 8];
  end

Best regards
Frank
 

[ShengN_Intel]

Hi Ranesh,

Below is the expert explanation on the second example (s_outbytecount):

s_output_data[d] <= s_in_data[((W_MODULE_DATA - ((d - s_outbytecount) * 8))- 1) -: 8]; //vector_capture_v2.sv, line number 151

In this case, array index uses logic type variable "s_outbytecount", for which synthesis generates a circuit which ensures no out of bound error happens.

In original use case, when local param is used in the index operation, they are replaced with actual values in compile time, so all possible indices get generated which cause out of bound error during loop unrolling.

e.g.

s_in_data[((W_MODULE_DATA - ((c - c_IN_DESC_BYTE_CNT) * 8)) - 1) -: 8] 

Here, c is running from 16 to 31. During loop unrolling, index value is generated for all values of c which causes out of range error.

If you need further detailed explanation, may be we can set up a meeting after January 3rd with internal expert where they can explain the concept of index range being known at compile time.

Thanks,

Best regards,

Sheng