Arrays issue

Altera_Forum · ‎01-31-2015

I've been trying to code arrays lately (verilog newbie) and I'm having issues reading values inside them.

Narrowed issue down to a small code sample:

module arrays(LEDG);
output LEDG;
reg array;
reg wat=0;
initial begin
    array=8'hff;
end
//assign LEDG=array;
assign LEDG=array;
endmodule

First (commented) assign will return the correct value (0xff), second one won't (returns 0x00).

Cannot understand why, is there something about arrays usage I missed out? Didn't find much info.

Using Quartus 13.0.1

Thanks

Altera_Forum · ‎01-31-2015

why not just assign LEDG to a constant?

assign LEDG[7:0] <= 8'hff;

Altera_Forum · ‎01-31-2015

It's just a small code snippet to illustrate the issue, I intend to fill variable values into the array in full project...

Altera_Forum · ‎01-31-2015

why not post the whole code then?