i am trying to use modelsim to simulate some chunks of a VHDL design which now include some FIFO modules ( the design also has PCIE, JESD cores and a whole bunch of other stuff )
I can compile the modules in modelsim ok until i get to modules that refer to the FIFO ip blocks ( the whole design compiles & fits fine in Quartus so is ok a a "thing" )
when I try and run the "Generate Simulator Setup Script for IP" and point it at the root of the project, it runs through but then complains that a bunch of modules in the PCIe back end do not have simulation profiles and fails to complete along the lines of
Error: 2021.11.08.14:21:15 Error: SPD file C:/final/pcie_ips/pcie_a10_hip_0_example_design/ip/pcie_example_design/fast_dac_onchip_ram_1\fast_dac_onchip_ram_1.spd not found. Please generate simulation files for IP file C:/final/pcie_ips/pcie_a10_hip_0_example_design/ip/pcie_example_design/fast_dac_onchip_ram_1.ip before generating simulator setup scripts.
but that actual entity is a custom created module wrapped around a DP RAM module so doesnt have any simulation options
I know i don't need to do the simulation library compiler thing as the twentnm library etc is there for the Arria 10 devices but I think until i can get the simulator script to run then I'm stuck on getting the FIFOs to be compiled in modelsim.
I did try manually trying to compile the bits I could see in the relevant sim folders where the FIFO instances were created directly in modelsim but couldnt get it happy
i would like not have to try and re-create a new project with the relevant source in it just to try and exclude these failing modules, so wondering if anyone has any pearls of wisdom of how to essentially exclude chunks of the design from the simulation script generator or something that will get me a running sim ?