Arria V clock no output dependent(15610)

[EBoln]

HI!

i am using arria v for a new project but ran into the following behavior:
- when I only use logic, the clock pin is synthesized successfully
- when I add video ip core to the project, then all the logic connected to this clock pin is not synthesized

Why? Project in attachments(i'm use Q18.1.1)

thank

P.S. on RTL viewer all is OK, but post-mapping clock network is absent

[JonWay_C_Intel]

Hi EBoln,

There is no attachment. If your project is huge, could you send us a simplified design that shows the problem. Thanks.

[EBoln · Accepted solution]

Found a bug in my custom qsys module, the reset was confused

[JonWay_C_Intel]

Thanks @EBoln  for sharing the root cause of the problem.