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Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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15474 Discussions

Arria V clock no output dependent(15610)

EBoln
New Contributor I
314 Views

HI!

i am using arria v for a new project but ran into the following behavior:
- when I only use logic, the clock pin is synthesized successfully
- when I add video ip core to the project, then all the logic connected to this clock pin is not synthesized

Why? Project in attachments(i'm use Q18.1.1)

thank

 

P.S. on RTL viewer all is OK, but post-mapping clock network is absent

0 Kudos
1 Solution
EBoln
New Contributor I
271 Views

Found a bug in my custom qsys module, the reset was confused

View solution in original post

3 Replies
JonWay_C_Intel
Employee
287 Views

Hi EBoln,

There is no attachment. If your project is huge, could you send us a simplified design that shows the problem. Thanks.

EBoln
New Contributor I
272 Views

Found a bug in my custom qsys module, the reset was confused

JonWay_C_Intel
Employee
265 Views

Thanks @EBoln  for sharing the root cause of the problem.

Reply