Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Is it possible to save the time of compilation (analysis/synthesis/fitting, doesn't matter) and date to some inner signal in VHDL (like the __TIME__ and __DATE__ C macros) , or by some other method in Quartus? I have searched the web and have not found any such thing. Yarden Tal.
you could try adding a post-flow Tcl script that could either edit the VHDL file directly and add date/time stamps or have the Tcl call a script/program that will add your desired string.
VHDL has no method of accessing things like time or anything else external to the code. The only way would be to set a constant using TCL like thepancake says.
Could you show me an example? I am clueless as to how to perform such an operation (I am, though, well versed in VHDL, yet not so much with TCL scripts). Thanks again :)
