Re: Basic setup in Quartus

Altera_Forum · ‎08-07-2015

Hi

i have demo project running on a eval board with a top.v file as entry. Now i have tried to make a new project to match a custom PCB but the generated top.v does look anything close to the other. so im guessing that im missing some configurations somewhere.

In my Qsys for both projects there is a NIOS-II processor,Altera_pll, adc, jtag,1sec timer,onchip memory.

In the pin planner is it possible to assign a "default" value to the pins or where is this done ? (im getting warning 10541 VHDL Signal Declaration warning: used implicit default value for signal)

This is my first time setting up a project so any help is appreciated. Been looking through the quartus manual but cant find anything helpful on this.

demo:

module top (     input clk,
    input reset,
    input  SW,
    output  LED
);
wire adc_10M_clk;
wire nios_50M_clk;
wire pll_locked;
wire reset_n;
assign reset_n = !reset;
    all_pll    alt_pll_inst (
   .areset ( reset ),
    .inclk0 ( clk ),
    .c0 ( adc_10M_clk ),
    .c1 ( nios_50M_clk),
    .locked ( pll_locked )
    );
    nios_setup u0 (
        .clk_clk                               (nios_50M_clk),                               //                            clk.clk
        .reset_reset_n                         (reset_n),                         //                          reset.reset_n
        .led_io_external_connection_export        (LED),    //    led_pio_external_connection.export
        .sw_io_external_connection_export         (SW), // switch_pio_external_connection.export
        .modular_adc_0_adc_pll_clock_clk       (adc_10M_clk),       //    modular_adc_0_adc_pll_clock.clk
        .modular_adc_0_adc_pll_locked_export   (pll_locked)    //   modular_adc_0_adc_pll_locked.export
    );
    
    
endmodule

New project:

// Copyright (C) 1991-2015 Altera Corporation. All rights reserved.// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, the Altera Quartus II License Agreement,
// the Altera MegaCore Function License Agreement, or other 
// applicable license agreement, including, without limitation, 
// that your use is for the sole purpose of programming logic 
// devices manufactured by Altera and sold by Altera or its 
// authorized distributors.  Please refer to the applicable 
// agreement for further details.
module top
(
// {ALTERA_ARGS_BEGIN} DO NOT REMOVE THIS LINE!
    ADC_7,
    ADC_8,
    ADC_PSB1,
    ADC_PSB2,
    ADC_PSB3,
    ADC_PSB4,
    ADC_Vc1,
    ADC_Vc2,
    BP_SW_1,
    BP_SW_2,
    CLK50M,
    EXT_ADC1_CLK,
    EXT_ADC1_CS,
    EXT_ADC1_DATA,
    EXT_ADC2_CLK,
    EXT_ADC2_CS,
    EXT_ADC2_DATA,
    GD_FB,
    LED,
    LVDS_det,
    LVDS_RD_MINUS,
    LVDS_RD_PLUS,
    LVDS_TD_MINUS,
    LVDS_TD_PLUS,
    PSB_ENA,
    PSB_FAIL,
    PWM_S,
    RS232_CTS,
    RS232_RTS,
    RS232_RX,
    RS232_TX,
    SEL1,
    SEL2,
    SEL3,
    TEMP_CAP1,
    TEMP_CAP2,
    TEMP_PCB,
    TEMP_SW,
    xBP_SW_1,
    xBP_SW_2,
    xEXT_ADC1_CLK,
    xEXT_ADC1_CS,
    xEXT_ADC1_DATA,
    xEXT_ADC2_CLK,
    xEXT_ADC2_CS,
    xEXT_ADC2_DATA,
    xGD_FB,
    xPSB_ENA,
    xPSB_FAIL,
    xPWM_S,
    xTEMP_CAP1,
    xTEMP_CAP2,
    xTEMP_SW
// {ALTERA_ARGS_END} DO NOT REMOVE THIS LINE!
);
// {ALTERA_IO_BEGIN} DO NOT REMOVE THIS LINE!
input            ADC_7;
input            ADC_8;
input            ADC_PSB1;
input            ADC_PSB2;
input            ADC_PSB3;
input            ADC_PSB4;
input            ADC_Vc1;
input            ADC_Vc2;
output            BP_SW_1;
output            BP_SW_2;
input            CLK50M;
output            EXT_ADC1_CLK;
output            EXT_ADC1_CS;
input            EXT_ADC1_DATA;
output            EXT_ADC2_CLK;
output            EXT_ADC2_CS;
input            EXT_ADC2_DATA;
input        GD_FB;
output        LED;
input            LVDS_det;
input            LVDS_RD_MINUS;
input            LVDS_RD_PLUS;
output            LVDS_TD_MINUS;
output            LVDS_TD_PLUS;
output            PSB_ENA;
input            PSB_FAIL;
output        PWM_S;
input            RS232_CTS;
output            RS232_RTS;
input            RS232_RX;
output            RS232_TX;
input            SEL1;
input            SEL2;
input            SEL3;
input            TEMP_CAP1;
input            TEMP_CAP2;
input            TEMP_PCB;
input        TEMP_SW;
output            xBP_SW_1;
output            xBP_SW_2;
output            xEXT_ADC1_CLK;
output            xEXT_ADC1_CS;
input            xEXT_ADC1_DATA;
output            xEXT_ADC2_CLK;
output            xEXT_ADC2_CS;
input            xEXT_ADC2_DATA;
input        xGD_FB;
output            xPSB_ENA;
input            xPSB_FAIL;
output        xPWM_S;
input            xTEMP_CAP1;
input            xTEMP_CAP2;
input        xTEMP_SW;
// {ALTERA_IO_END} DO NOT REMOVE THIS LINE!
// {ALTERA_MODULE_BEGIN} DO NOT REMOVE THIS LINE!
// {ALTERA_MODULE_END} DO NOT REMOVE THIS LINE!
endmodule

Altera_Forum · ‎08-10-2015

You need to instantiate your Nios in the top.v for your new development board. I've done so as an example below.

It looks like your new board has a 50MHz oscillator on it, this is common. So, there's (probably) no need for your PLL. I've removed and just fed your Nios with the 50MHz clock.

LED connections are straightforward. I've assumed SEL1-3 are switches on your new dev board (I don't recognise the I/O signal list you posted - which development board is it for?). If they're not you'll need to substitute in signals that are switches (or push buttons perhaps?).

I'm not sure why your Nios module would need the 10MHz clock and you should be able to ignore the PLL locked signal you had before - see comments in code.

I've not compiled the code - it's just provided for guidance. Let me know how you get on.

Cheers,

Alex

module top
(
// {ALTERA_ARGS_BEGIN} DO NOT REMOVE THIS LINE!
    ADC_7,
    ADC_8,
    ADC_PSB1,
    ADC_PSB2,
    ADC_PSB3,
    ADC_PSB4,
    ADC_Vc1,
    ADC_Vc2,
    BP_SW_1,
    BP_SW_2,
    CLK50M,
    EXT_ADC1_CLK,
    EXT_ADC1_CS,
    EXT_ADC1_DATA,
    EXT_ADC2_CLK,
    EXT_ADC2_CS,
    EXT_ADC2_DATA,
    GD_FB,
    LED,
    LVDS_det,
    LVDS_RD_MINUS,
    LVDS_RD_PLUS,
    LVDS_TD_MINUS,
    LVDS_TD_PLUS,
    PSB_ENA,
    PSB_FAIL,
    PWM_S,
    RS232_CTS,
    RS232_RTS,
    RS232_RX,
    RS232_TX,
    SEL1,
    SEL2,
    SEL3,
    TEMP_CAP1,
    TEMP_CAP2,
    TEMP_PCB,
    TEMP_SW,
    xBP_SW_1,
    xBP_SW_2,
    xEXT_ADC1_CLK,
    xEXT_ADC1_CS,
    xEXT_ADC1_DATA,
    xEXT_ADC2_CLK,
    xEXT_ADC2_CS,
    xEXT_ADC2_DATA,
    xGD_FB,
    xPSB_ENA,
    xPSB_FAIL,
    xPWM_S,
    xTEMP_CAP1,
    xTEMP_CAP2,
    xTEMP_SW
// {ALTERA_ARGS_END} DO NOT REMOVE THIS LINE!
);
// {ALTERA_IO_BEGIN} DO NOT REMOVE THIS LINE!
input            ADC_7;
input            ADC_8;
input            ADC_PSB1;
input            ADC_PSB2;
input            ADC_PSB3;
input            ADC_PSB4;
input            ADC_Vc1;
input            ADC_Vc2;
output           BP_SW_1;
output           BP_SW_2;
input            CLK50M;
output           EXT_ADC1_CLK;
output           EXT_ADC1_CS;
input            EXT_ADC1_DATA;
output           EXT_ADC2_CLK;
output           EXT_ADC2_CS;
input            EXT_ADC2_DATA;
input       GD_FB;
output      LED;
input            LVDS_det;
input            LVDS_RD_MINUS;
input            LVDS_RD_PLUS;
output           LVDS_TD_MINUS;
output           LVDS_TD_PLUS;
output           PSB_ENA;
input            PSB_FAIL;
output      PWM_S;
input            RS232_CTS;
output           RS232_RTS;
input            RS232_RX;
output           RS232_TX;
input            SEL1;
input            SEL2;
input            SEL3;
input            TEMP_CAP1;
input            TEMP_CAP2;
input            TEMP_PCB;
input       TEMP_SW;
output           xBP_SW_1;
output           xBP_SW_2;
output           xEXT_ADC1_CLK;
output           xEXT_ADC1_CS;
input            xEXT_ADC1_DATA;
output           xEXT_ADC2_CLK;
output           xEXT_ADC2_CS;
input            xEXT_ADC2_DATA;
input       xGD_FB;
output           xPSB_ENA;
input            xPSB_FAIL;
output      xPWM_S;
input            xTEMP_CAP1;
input            xTEMP_CAP2;
input       xTEMP_SW;
// {ALTERA_IO_END} DO NOT REMOVE THIS LINE!
// {ALTERA_MODULE_BEGIN} DO NOT REMOVE THIS LINE!
// {ALTERA_MODULE_END} DO NOT REMOVE THIS LINE!
wire       nios_50M_clk;
wire       reset_n;
wire  LED_ctrl_from_nios;
wire  SW_to_nios;
assign nios_50M_clk = CLK50M;             // Local 50MHz osc on your new board means you don't need your 10MHz->50MHz PLL
assign reset_n = 1'b1;                    // Just tie reset_n high to take Nios out of reset from the start
assign LED = LED_ctrl_from_nios;     // Connect 3 LEDs to your control from your Nios
assign LED = 5'b0;                   // Tie off unused LEDs
assign SW_to_nios = {SEL3, SEL2, SEL1};   // A guess, assuming SEL1-3 are switches on your dev board. If not you will need to find some.
         // Instanciate your Nios module inside the outer 'top' wrapper module for your new dev board.
   nios_setup u0 (
      .clk_clk                               (nios_50M_clk),         //                            clk.clk
      .reset_reset_n                         (reset_n),              //                          reset.reset_n
      .led_io_external_connection_export     (LED_ctrl_from_nios),   //    led_pio_external_connection.export
      .sw_io_external_connection_export      (SW_to_nios),           // switch_pio_external_connection.export
            // Suspect you don't need the following two lines for your application. Either tie off (as below)
            //   or revisit in Qsys and modify your component to remove them.
      .modular_adc_0_adc_pll_clock_clk       (1'b0),                 //    modular_adc_0_adc_pll_clock.clk
      .modular_adc_0_adc_pll_locked_export   (1'b0)                  //   modular_adc_0_adc_pll_locked.export
    );
endmodule

Altera_Forum · ‎08-10-2015

Hi Alex thanks for the help...

I was hoping the Pin Planner auto generated top level file could be used. I've specified both the PLL and the NiosII system in there as IP- components...But if they don't add them to the Top level file whats the point in that ?

/stefan

Altera_Forum · ‎08-10-2015

hi could you show me the NIOS part in VHDL ? /thanks

Altera_Forum · ‎08-10-2015

Hi Alex

Just been reading on the "Altera Modular ADC core" IP found in Qsys the ADC runs at 1MHz and clock must be a factor of 2,10,20,40 or 80, so why would i go without the PLL to generate the 10MHz clock ?

/stefan

Altera_Forum · ‎08-10-2015

Yes, the auto-generated top level file can be used, but it's only a template containing all the I/O you've specified. It will not contain any design information.

You mention you have a Qsys project for both projects. So, when you generated that for your custom board, that will create a '{my_design}.v' file in a '{my_design}/synthesis' sub-directory in your project folder (where '{my_design}' matches the name of your Qsys '{my_design}.qsys' project file in your project directory). You need to instantiate that into your 'top.v' file that the Pin Planner generated for you. That's more or less what I did for you before but I had to guess a little based on the info you posted.

Yes, you'll need a 10MHz clock for the ADC. So, if your custom board has a 50MHz clock source you're going to have to generate the 10MHz - I recommend using a PLL.

--- Quote Start ---

could you show me the NIOS part in VHDL...

--- Quote End ---

Everything you've posted has been Verilog. I suggest you stick with one HDL for the time being.

If you're still struggling attach the '{my_design}.v' file to this post and I'll have a look in conjunction with the 'top.v' I/O wrapper file that you posted previously.

Cheers,

Alex

Altera_Forum · ‎08-11-2015

Hi Alex

thanks a lot...ill have a look at it..

/stefan

Altera_Forum · ‎08-11-2015

Hi Alex

so i guess this vhdl taken from {My_custom}/syntesis/{My_custom.vhd}

--entity CellController is
	--port (
	--	clk_clk                             : in  std_logic                    := '0'; --                          clk.clk
	--	leds_external_connection_export     : out std_logic_vector(3 downto 0);        --     leds_external_connection.export
	--	modular_adc_0_adc_pll_clock_clk     : in  std_logic                    := '0'; --  modular_adc_0_adc_pll_clock.clk
	--	modular_adc_0_adc_pll_locked_export : in  std_logic                    := '0'; -- modular_adc_0_adc_pll_locked.export
	--	reset_reset_n                       : in  std_logic                    := '0'  --                        reset.reset_n
	--);
--end entity CellController;

needs to fit into auto generated top.vhd

-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, the Altera Quartus II License Agreement,
-- the Altera MegaCore Function License Agreement, or other 
-- applicable license agreement, including, without limitation, 
-- that your use is for the sole purpose of programming logic 
-- devices manufactured by Altera and sold by Altera or its 
-- authorized distributors.  Please refer to the applicable 
-- agreement for further details.
library ieee;
use ieee.std_logic_1164.all;
library altera;
use altera.altera_syn_attributes.all;
entity top is
	port
	(
-- {ALTERA_IO_BEGIN} DO NOT REMOVE THIS LINE!
		PSB_ENA : in std_logic;
		ADC_PSB1 : in std_logic;
		ADC_PSB2 : in std_logic;
		ADC_PSB3 : in std_logic;
		ADC_PSB4 : in std_logic;
		ADC_Vc1 : in std_logic;
		ADC_Vc2 : in std_logic;
		ADC_7 : in std_logic;
		ADC_8 : in std_logic;
		RS232_RX : in std_logic;
		RS232_CTS : in std_logic;
		EXT_ADC2_DATA : in std_logic;
		SEL1 : in std_logic;
		xEXT_ADC2_CS : in std_logic;
		xEXT_ADC2_CLK : in std_logic;
		xEXT_ADC1_CS : in std_logic;
		xBP_SW_2 : in std_logic;
		xBP_SW_1 : in std_logic;
		EXT_ADC1_CS : in std_logic;
		EXT_ADC1_CLK : in std_logic;
		xPSB_ENA : in std_logic;
		TEMP_CAP2 : in std_logic;
		TEMP_CAP1 : in std_logic;
		PSB_FAIL : in std_logic;
		SEL3 : in std_logic;
		EXT_ADC1_DATA : in std_logic;
		xPSB_FAIL : in std_logic;
		TEMP_PCB : in std_logic;
		SEL2 : in std_logic;
		RS232_TX : in std_logic;
		RS232_RTS : in std_logic;
		BP_SW_2 : in std_logic;
		BP_SW_1 : in std_logic;
		EXT_ADC2_CLK : in std_logic;
		EXT_ADC2_CS : in std_logic;
		xEXT_ADC2_DATA : in std_logic;
		xTEMP_CAP2 : in std_logic;
		xTEMP_CAP1 : in std_logic;
		xEXT_ADC1_DATA : in std_logic;
		nios_setup_clk_clk : in std_logic;
		nios_setup_led_io_external_connection_export : in std_logic_vector(7 downto 0);
		nios_setup_modular_adc_0_adc_pll_clock_clk : in std_logic;
		nios_setup_modular_adc_0_adc_pll_locked_export : in std_logic;
		nios_setup_reset_reset_n : in std_logic;
		alt_pll_areset : in std_logic;
		alt_pll_inclk0 : in std_logic;
		alt_pll_c0 : out std_logic;
		alt_pll_c1 : out std_logic;
		alt_pll_locked : out std_logic;
		LVDS_det : in std_logic;
		xEXT_ADC1_CLK : in std_logic;
		LVDS_RD : in std_logic;
		LVDS_TD : in std_logic;
		PWM_S : in std_logic_vector(0 to 3);
		GD_FB : in std_logic_vector(0 to 3);
		TEMP_SW : in std_logic_vector(0 to 3);
		xGD_FB : in std_logic_vector(0 to 3);
		xPWM_S : in std_logic_vector(0 to 3);
		xTEMP_SW : in std_logic_vector(0 to 3)
-- {ALTERA_IO_END} DO NOT REMOVE THIS LINE!
	);
-- {ALTERA_ATTRIBUTE_BEGIN} DO NOT REMOVE THIS LINE!
-- {ALTERA_ATTRIBUTE_END} DO NOT REMOVE THIS LINE!
end top;
architecture ppl_type of top is
-- {ALTERA_COMPONENTS_BEGIN} DO NOT REMOVE THIS LINE!
component alt_pll
	port
	(
		areset 	: in std_logic;
		inclk0 	: in std_logic;
		c0 		: out std_logic;
		c1 	 	: out std_logic;
		locked 	: out std_logic
	);
end component;
-- {ALTERA_COMPONENTS_END} DO NOT REMOVE THIS LINE!
begin
-- {ALTERA_INSTANTIATION_BEGIN} DO NOT REMOVE THIS LINE!
alt_pll_inst : alt_pll
	port map
	(
		areset => alt_pll_areset,
		inclk0 => alt_pll_inclk0,
		c0 	 => alt_pll_c0,
		c1 	 => alt_pll_c1,
		locked => alt_pll_locked
	);
-- {ALTERA_INSTANTIATION_END} DO NOT REMOVE THIS LINE!
end;

im not sure how the clock should be mapped, as of now i mapped nios_setup_clk_clk to (IO_bank2, pin 27)in the pin planner but i should also be mapped to the PLL.

ive added a PLL IP-component in the Quartus project and in the Pin-planner but not in Qsys, hope this is correct.

thanks in advance...

/stefan

Altera_Forum · ‎08-11-2015

Hi Alex just to let you know i think ive solved this part of the problem.

here's the last part of my top level entry.


architecture ppl_type of top is
signal adc_10MHz_clk:	 	std_logic;
signal nios_50MHz_clk:	 	std_logic;
signal pll_locked:	 	std_logic;
signal reset_n:		 	std_logic;
component alt_pll
	port
	(
		areset 	: in std_logic;
		inclk0 	: in std_logic;
		c0 	: out std_logic;
		c1 	: out std_logic;
		locked 	: out std_logic
	);
end component;
component CellController
port
	(
		clk_clk                             : in  std_logic; --                          clk.clk
		leds_external_connection_export     : out std_logic_vector(3 downto 0); --     leds_external_connection.export
		modular_adc_0_adc_pll_clock_clk     : in  std_logic; --  modular_adc_0_adc_pll_clock.clk
		modular_adc_0_adc_pll_locked_export : in  std_logic; -- modular_adc_0_adc_pll_locked.export
		reset_reset_n                       : in  std_logic  --                        reset.reset_n
	);
end component;
begin
alt_pll_inst : alt_pll
	port map
	(
		areset => reset_in,
		inclk0 => clk_in_50MHz,
		c0 	 => adc_10MHz_clk,
		c1 	 => nios_50MHz_clk,
		locked => pll_locked
	);
	
CellController_inst : CellController
	port map
	(
			clk_clk                        => nios_50MHz_clk,
			leds_external_connection_export     => LED(3 downto 0),
			modular_adc_0_adc_pll_clock_clk     => adc_10MHz_clk,
			modular_adc_0_adc_pll_locked_export => pll_locked,
			reset_reset_n                       => reset_n	
	);
end;

now there is just some issues with unconstrained inputs...

thanks for the help