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17268 Discussions

Big Problems with bidir Pin :-)

Altera_Forum
Honored Contributor II
‎05-23-2007 07:12 PM
2,185 Views

Hello, 

 

I have a problem with the bidir pins in Quartus II. 

 

I made a simple project to demonstrate this. 

 

http://rapidshare.com/files/32982986/iobuff_test.zip.html (http://rapidshare.com/files/32982986/iobuff_test.zip.html) 

 

If oe=1, the value on "in" (which is alleways '1') should be going to "io". 

 

In the simulation you see, that the simulator generates a new variable called "io~result". This variable has the right value, which the bidirectinal pin also should have. 

But the bidir pin "io" allways stay "undefined". Why??? 

 

I searched for other examples with this pin but I can't find them. 

Is there no way to work with I/Os? 

 

It would be gratefull if someone has s solution, or better an example to handle bidirectinal pins. 

 

Regards, 

Chrisitan
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Altera_Forum
Honored Contributor II
‎05-24-2007 01:52 AM
1,479 Views

When QII simulator simulates the bidirectional pin (e.g. your bidirectional pin name is bidir_io), it will automatically create the bidir_io~result. bidir_io represents the input channel of the bidirectional pin and bidir_io~result represents the output channel of the bidirectional pin.  

 

Therefore your bidir_io~result displays the correct output when OE=1. As for why bidir_io is X is because you do not set any input vector to it. In short, the QII simulator breaks the bidirectional pin to input (e.g bidir_io) and output (e.g. bidir_io~result) in the simulation waveform. 

 

Hope it helps.
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Altera_Forum
Honored Contributor II
‎05-24-2007 12:11 PM
1,479 Views

Hello, 

thank you for your reply. 

 

It's a good explanation for the added variable. 

 

So, I made a new vwf-file to test this, besides I erased the clock, because I don't net it. 

The new project: http://rapidshare.com/files/33104146/iobuff_test.zip.html (http://rapidshare.com/files/33104146/iobuff_test.zip.html) 

 

The VHDL Code works this way, that if oe='0' the value I set to "io" is shown on the output. 

But then I want the value on input to be shown on io~result. I set oe='1' and the value on "io" to "DC" (Don't Care). 

 

On the simulation you see, that the value an io~result (which should be the same linke "in") is unknown. 

I have no idea why this value is unknown. It should work like described in the VHDL Code. 

 

It makes no sense to give "io" another value for the time oe='1' because this value will be the same like on io~result. 

 

Best regards, 

Christian
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