Blacl Box synthesis attribute

[Altera_Forum]

Im trying to tell the Quartus 2 synthesiser that my component is a black box so it doesnt complain that it cant find the entity declaration. Ive tried all of the following in the VHDL top level:  

 attribute syn_black_box, black_box, noopt : boolean ; attribute (whatever) of my_comp : component is true;   None of them seem to work and when I go through analysis and elaboration is complains it cant find the entity for "my_comp". what is the correct attribute to use?

[Altera_Forum]

How do you physically want it to place-and-route a black-box? (I ask because until recently, you really couldn't do a black-box) 

 I create the normal entity and then do: architecture bb of entityname is begin end bb;  So there's nothing in it. I then run analysis and elaboration to get the hierarchy, right-click on this hierarchy in the hierarchy browser and create a partition. Then I open Assignments -> Design Partitions Window and set that partition to Empty.

[Altera_Forum]

I dont want to P&R it, I just want to synthesise with a black box in place. 

 This isnt the entire TL as a black box - a component called at the top level I want to be a black box (so other stuff is synthesized, this component isnt, for now).

[Altera_Forum]

That flow works for synthesis and P&R. I don't know what happens if you don't add the empty partition assignment, i.e. if it keeps all the port connections or rips out everything since they don't drive anything. It might keep them, but not sure. If you have the web edition, I don't think you have incremental compilation/partition access, but if you do it's real easy to add that in.