Hi, I am an engineering student running the Quartus Prime Lite edition for a digital clock assignment. I'm having some questions about different types of design files. One of the components is written in a Verilog HDL file and works just fine in simulation when compiled alone. Every digit is outputing correctly by this step. But when I combined it with other componets in a Block Diagram, it stoped working, outputing uncertain values all the time. Moreover, it still wouldn't work even if I created a dedicated Block Diagram and tied the exact input and output pins to the corresponding ports. The outputs are still random values. Pins connections and simulation results are shown in the pictures attached below. I've been searching online for quite some time and got little clue of what's happening here. Any advice at this point would be greatly appreciated!
Quartus Prime Lite Edition Version 18.1.0
Do you mind to attach the project.qar file for us to look into your design?
Besides, it is recommended to design the project using Verilog HDL or VHDL instead of BDF and run simulation in Questa or Modelsim instead of running simulation in VWF. Because there is a bug in running simulation in VWF, sometimes it does not work.
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