Board Support Package for OpenCL

[Altera_Forum]

Hi, 

 Our university has two older boards that I want to use for FPGA-based OpenCL. The first board is an Altera/terasIC DE4-530 Stratix IV Development Board and an Altera Arria V GT. I downloaded Quartus v17.0 and the corresponding OpenCL SDK. There seems to be no BSP for these boards. Are they available? Has anyone created a custom BSP for these boards? I really want to use these boards for a research project and we just don't have the resources to purchase new boards. I need a large LE size for the problem-set I want to solve...  Thanks,  QG

[Altera_Forum]

The only boards with existing official OpenCL support are the Stratix V and Arria 10 reference boards from Altera and a few boards from Terasic, Bittware, Nallatech and Gidel which are also mostly based on Stratix V, Arria 10 and Cyclone V SoCs. The two boards you mentioned more than likely do not have existing support for OpenCL. Creating an OpenCL BSP is not at all a simple task and can only be done by people with years of experience in hardware design and hence, only companies that can sell a lot of boards will attempt to spend resources on creating a BSP for their boards. 

 Altera has reference BSPs for Stratix V, Arria 10 and Cyclone V and building custom BSPs on top of those for custom boards with similar specs is possible, but creating a BSP for a custom board from scratch, without having a reference BSP, would be next to impossible for the average FPGA programmer.  P.S. You can join Altera's university program and see if you can get a reference Stratix V or Arria 10 board donated to you.

[Altera_Forum]

Thanks for the response. I also found a stratix v gx fpga development kit (https://www.altera.com/products/boards_and_kits/dev-kits/altera/kit-sv-gx-host.html). Seems I can use that. Does the s5_ref BSP work with this board? Or should I approach Intel/Altera for a BSP? 

 https://www.altera.com/content/dam/altera-www/global/en_US/images/products/devkits/altera/images/stratixv_fpga_board.jpg

[Altera_Forum]

That is one their Stratix V reference boards, though I am not sure if it will work with the reference BSP. The FPGA listed in the hardware specs of their BSP is "5sgsed8k2f40c2", but I cannot find any development kits from Altera with that FPGA on it. The reference BSP is included in all recent versions of Quartus. Try to see if the BSP works with your board by compiling the hello_world OpenCL example and running it on the board. If it didn't, you can contact Altera directly and see if they have a BSP for that specific board.

[Altera_Forum]

The good folks at Terasic and Altera/Intel came to the rescue. Terasic provided me with an old version of the DE4-530 OpenCL BSP for 11.0 of Quartus and Altera/Intel provided me with an older version of the BSP for the Stratix V GX that seems to work for 16.0 of Quartus! Unfortunately, I gave them the wrong board number :oops:. It was supposed to be the Stratix V Advanced Systems Development Kit. So, now I have to go back and ask them for the right BSP. There seems to be a PD version of the BSP for Arria V GX board that seems to work for V15.0 of Quartus. Modifying that to work with the Arria V GT shouldn't be a problem.  

 https://www.altera.com/content/dam/altera-www/global/en_US/images/products/devkits/altera/images/sv_advanced_sys_board.jpg

[Altera_Forum]

Interesting; so these people have some unreleased/private BSPs that they would make available to public upon request.

[Altera_Forum]

The DE4 board was the first board they used with doing the compiler in 2012-13. If you look in hdl/ip you will see all the built-in functions that are used by the compiler. These ip may call out megawizards for use by the compiler. Supporting a device family is a lot of work so they don't support the S4 anymore. The s5_ref is a board that had lots of resources so they use that board as a reference as you can rip out what your board does not use. Mainly when porting you have to get the memories and PCIe pin numbers correct and then do a good layout and keep floating out of the center. The s5_ref has PCIe, DDR3. There is a s5_net that also has QDRII, and channels for ethernet connections. If you are just looking for a board to learn OpenCL on try a c5soc board. They're fun!

[Altera_Forum]

--- Quote Start ---   If you are just looking for a board to learn OpenCL on try a c5soc board. They're fun!   --- Quote End ---    Frankly, an FPGA board would not be my first preference for learning OpenCL! I just don't understand how a company can charge thousands of dollars on hardware (and thousands of dollars for the software) and not provide board support packages for their own boards. For OpenCL, I would much rather purchase an AMD board for far less that has 100% OpenCL 1.2 support out-of-the-box. The problem set I was planning on doing was more for speedup comparisons against a GPU/CPU implementation. This whole experience is just disheartening for an FPGA neophyte like myself...  PS: I understand the cost involved in doing this, but the best person to write these BSPs are the engineers/company that manufactured the board if this is the technology they want to promote...

[Altera_Forum]

I would venture the most users of these boards are NOT using them for OpenCL use, but rather for FPGA code development in Verilog/VHDL. For OpenCL I would likely just go for a high-end graphics card that has an OpenCL package rather than an FPGA board.

[Altera_Forum]

The limited availability of OpenCL support on FPGAs is most certainly not aimed at new learners, I am afraid. The current OpenCL support is aimed at long-time FPGA developers to help them reduce development time, and long-time OpenCL developers with no hardware knowledge who now at least have the possibility of using FPGAs.

[Altera_Forum]

The main reason to use OpenCL is to avoid the usage of VHDL/Verilog for FPGA development and bringing it more into the mainstream development as you indicated HRZ. With over 30 years of software product development, I would not sell a product to my clients knowing that they would need to go through hoops and hurdles to get my software running, especially after charging them thousands of dollars for it (our software costs hundreds of thousands of dollars!).  

 Of course, for OpenCL learning purposes, it doesn't make sense to use FPGAs. There are far better hardware (CPUs, GPUs, etc.) for that purpose as I indicated earlier. However, my primary purpose was in fact to run my project on an FPGA hardware as opposed to the GPU/CPU. Now I find myself needing to use VHDL/Verilog to do that purpose (or try to get Altera/Intel to donate a board to the University)...

[Altera_Forum]

For university work, you can easily get free licenses as part of Altera's university program. Getting board donations might be a little bit harder but you can get big discounts just by being part of the university program. There are also always the OpenCL-capable Cyclone V SoCs which are dirt cheap (sub 100$), but of course don't have much to offer in terms of performance compared to Stratix V/Arria 10.

[Altera_Forum]

--- Quote Start ---   PS: I understand the cost involved in doing this, but the best person to write these BSPs are the engineers/company that manufactured the board if this is the technology they want to promote...  --- Quote End ---    Here is where it starts to get interesting. In the board support you can put ultra-efficient Verilog code in the BSP and then call that out from OpenCL. I realize that someone who just wants to learn OpenCL might as well download the Intel Processor OpenCL SDK. But if you want to know about reconfigurable computing this is the way to go. In the FPGA version you need to think about how to pipeline your code because that's when the FPGA gets the most powerful performance. OpenCL on FPGAs is not for the beginner. Nothing on FPGAs are for beginners. Power users only at this time. When the FPGA manufactures decide to make it easy it will be but they have to change their devices and basic software to make this work for the beginner.

[Altera_Forum]

and on top of that, they charge anyone who wants to even think about writing a BSP for OpenCL $700 for their class! >:-( 

 https://www.altera.com/support/training/course/iopnclbsp.html

[Altera_Forum]

You don't really need to attend that class, there are very detailed documents about how you can develop your own BSP based on the reference BSPs: 

 https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/opencl-sdk/ug_aocl_s5_net_platform.pdf https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/opencl-sdk/ug-aocl-altera-a10pciedk-platform.pdf https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/opencl-sdk/ug_aocl_c5soc_devkit_platform.pdf  Still, as I mentioned earlier, doing so requires considerable knowledge and experience about Quartus, QSYS, Network/PCI-E/DDR interfaces, Timing Closure, Partial Reconfiguration, etc., which not everyone has; without this knowledge and experience, even if you attend that class (or any other class), it won't help you much.