Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
17268 Discussions

Both 400G and 200G hard IP usage simultaneously

AlirezaTabesh
Beginner
2,186 Views

I am trying to utilize 10 XCVRs inside an F-tile. The FPGA that I am using contains four F-tiles; however, due to some constraints, I am obligated to have all the XCVRs in one F-tile. As the PMA width for my Direct PMA IPs are 64 bits, I am using more than 16 EMIBs in my F-tile. A way that I just found is to use both 400G and 200G hard IPs to expand my access to more streams. Does anyone know a way I can do that? I have been looking up and reading user guides, and still no luck!

I am attaching the F-tile architecture user guide to this message.

Labels (1)
0 Kudos
2 Replies
ZiYing_Intel
Employee
2,040 Views

Hi,

 

You may use this F-tile channel placement tool to check whether the topology is available.

 

Best regards,

zying

0 Kudos
ZiYing_Intel
Employee
1,971 Views

Hi,


Since no hear any feedback from you, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread.


Best regards,

zying


0 Kudos
Reply