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Bounding Question "Right Bound must be a constant"


I am currently building an n-bit shifter using VHDL. I have the code working in modelsim where it compiles just fine. But as soon as I try to bring it over to Quartus it gives the error: Error (10454): VHDL syntax error at barrel_shifter.vhd(68): right bound of range must be a constant

My code is:


library IEEE;
use IEEE.STD_Logic_1164.ALL;
use IEEE.numeric_std.all;


entity barrel_shifter is
generic (
bit_depth :integer := 8);
port (
A : out std_logic_vector(bit_depth-1 downto 0);
I : in std_logic_vector(bit_depth-1 downto 0);
S : in std_logic_vector(1 downto 0);
shift : in integer range 0 to bit_depth-1;
reset : in std_logic;
clk : in std_logic);
end barrel_shifter;


architecture behavior of barrel_shifter is

signal A_reg : std_logic_vector(bit_depth-1 downto 0);
signal Mux_out : std_logic_vector(bit_depth-1 downto 0);
signal rshift : std_logic_vector(bit_depth-1 downto 0);
signal lshift : std_logic_vector(bit_depth-1 downto 0);
signal shiftamt : integer range 0 to bit_depth-1;
--signal shift_reg : integer range 0 to bit_depth-1;

--assign output to registered value
A <= A_reg;
shiftamt <= shift;
Mux_proc : process (I, S, A_reg, rshift, lshift)
case S is
when "00" => --hold
Mux_out <= A_reg;
when "01" => --right shift
Mux_out <= rshift;
when "10" => --left shift
Mux_out <= lshift;
when "11" => --load/insert
Mux_out <= I;
when others => --always include an "error" state!
Mux_out <=(others => 'X');
end case;
end process Mux_proc;
reg_proc : process(clk)
if(rising_edge(clk)) then
if(reset = '0') then
A_reg <= (others=> '0');
A_reg <= Mux_out;
end if;
end if;
end process reg_proc;

rightshift : process(A_reg, shiftamt, rshift)
variable rs : std_logic_vector(bit_depth-1 downto 0);
variable shiftr : integer range 0 to bit_depth-1;
rs := A_reg;
shiftr := shiftamt;
for i in 0 to shiftr-1 loop
rs := rs(0) & rs(bit_depth-1 downto 1);
end loop;
--rs := rs(shiftamt-1 downto 0) & rs(bit_depth-1 downto shiftamt);
rshift <= rs;
end process rightshift;


leftshift : process(A_reg, shiftamt, lshift)
variable ls : std_logic_vector(bit_depth-1 downto 0);
ls := A_reg;
for i in 0 to shiftamt-1 loop
ls := ls(bit_depth-2 downto 0) & ls(bit_depth-1);
end loop;
--ls := ls(bit_depth-shiftamt-1 downto 0) & ls(bit_depth-1 downto bit_depth-shiftamt);
lshift <= ls;
end process leftshift;

end behavior;



Now I know the error is because "shiftamt" needs to be a constant but I thought declaring it as an integer could solve this. I am pretty rusty at this and honestly VHDL is not my strong suit. Does anyone have any ideas on how to fix the complication error while still maintaining that shiftamt can be changed? All of this is read in from a .csv file currently.

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2 Replies
Honored Contributor III

It's not clear which line is line 68 from the way you posted, but I think you should be using the variable you created, shiftr, in the process instead of shiftamt.

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Any update on this?

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