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Altera_Forum
Honored Contributor I
1,074 Views

Buffering a signal.

I'd like to understand. Suppose I do so 

signal_1 <= signal_0; signal_2 <= signal_1;  

if signal_0 is '1' on the first clock and '0' on the second - does signal_2 keep its value for two clocks?
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8 Replies
Altera_Forum
Honored Contributor I
75 Views

Hi,  

 

It depends on where do you put those lines.  

1. If you put this in clocked process like this 

process(reset_n, clk0) begin if reset_n='0' then signal_1_synch <= '0'; signal_2_synch <= '0'; elsif (clk0'event and clk0 = '1') then signal_1_synch <= signal_0_synch; signal_2_synch <= signal_1_synch; end if; end process; 

 

signal_2_synch will be 2 clock cyle delayed version of signal_0_synch. 

 

2. If you write outside clocked proces like this  

signal_1 <= signal_0; signal_2 <= signal_1; 

 

signal_2 would be same as signal_0.  

 

Se image attached image:  

https://www.alteraforum.com/forum/attachment.php?attachmentid=13296  

 

So no it will not keep its value for two clock cycles.
Altera_Forum
Honored Contributor I
75 Views

I see. Thank you. 

One more question. Is it valid to do so? 

process(reset_n, clk0) begin if reset_n='0' then signal_1_synch <= '0'; signal_2_synch <= '0'; elsif (clk0'event and clk0 = '1') then signal_1_synch <= signal_0_synch; signal_2_synch <= signal_1_synch; signal_0_synch <= '0'; end if; end process;  

I need to reset signal_0_synch immediately and keep value of signal_2_synch for 2 clocks.
Altera_Forum
Honored Contributor I
75 Views

 

--- Quote Start ---  

I see. Thank you. 

One more question. Is it valid to do so? 

[snip] 

I need to reset signal_0_synch immediately and keep value of signal_2_synch for 2 clocks. 

--- Quote End ---  

 

 

It depends where signal_0_synch comes from. If this is the only process it is driven from then yes, assuming it does something else as otherwise it will always just be '0'. 

If it is driven elsewhere then no, its not valid as it's like connecting two wires together and you get multiple driver errors and unknowns in your simulation.
Altera_Forum
Honored Contributor I
75 Views

 

--- Quote Start ---  

It depends where signal_0_synch comes from. If this is the only process it is driven from then yes, assuming it does something else as otherwise it will always just be '0'. 

If it is driven elsewhere then no, its not valid as it's like connecting two wires together and you get multiple driver errors and unknowns in your simulation. 

--- Quote End ---  

 

 

I see. So it could be something like this? 

process(reset_n, clk0) begin if reset_n='0' then signal_1_synch <= '0'; signal_2_synch <= '0'; elsif (clk0'event and clk0 = '1') then case cond is when 1 => ------------ when 2 => signal_0_synch <= '1'; end case; signal_1_synch <= signal_0_synch; signal_2_synch <= signal_1_synch; signal_0_synch <= '0'; end if; end process;  

This way I store the signal_0_synch and reset it. I need some buffer for another process to read the signal. If I reset it to quick It might be missed by other process.
Altera_Forum
Honored Contributor I
75 Views

That will not work. Your signal_0_synch will never be '1', because signal_0_synch will be assigned two times at same clock cycle (one in case statement and in last line). Try to explain what you are trying to do including more details.

Altera_Forum
Honored Contributor I
75 Views

 

--- Quote Start ---  

That will not work. Your signal_0_synch will never be '1', because signal_0_synch will be assigned two times at same clock cycle (one in case statement and in last line). Try to explain what you are trying to do including more details. 

--- Quote End ---  

 

I need a signal (flag) to communicate between two processes. One process set the flag, the other reads it. But the flag should be reset as soon as possible cause the second process will enter a loop always reading the flag='1'. I need a mini pipeline - a sgnal passes its value on and reset. Value lasts for 2 clock, quite enough not to miss it.
Altera_Forum
Honored Contributor I
75 Views

A signal set under clock edge control (= a flip-flop) can be active for one clock period, but not shorter. Activation for one clock cycle can be e.g. achieved by sorting your code like this: 

 

elsif (clk0'event and clk0 = '1') then signal_0_synch <= '0'; case cond is when 1 => ------------ when 2 => signal_0_synch <= '1'; end case; signal_1_synch <= signal_0_synch; signal_2_synch <= signal_1_synch; end if; 

 

Consider that all registered signals are updated after all assignments scheduled at the respective clock edge have been made. If a signal is only assigned once, the assignment order in the sequential code doesn't matter. But if you have multiple assignments to the same signal in a process, the last assignment wins.
Altera_Forum
Honored Contributor I
75 Views

 

--- Quote Start ---  

A signal set under clock edge control (= a flip-flop) can be active for one clock period, but not shorter. Activation for one clock cycle can be e.g. achieved by sorting your code like this: 

 

elsif (clk0'event and clk0 = '1') then signal_0_synch <= '0'; case cond is when 1 => ------------ when 2 => signal_0_synch <= '1'; end case; signal_1_synch <= signal_0_synch; signal_2_synch <= signal_1_synch; end if; 

 

Consider that all registered signals are updated after all assignments scheduled at the respective clock edge have been made. If a signal is only assigned once, the assignment order in the sequential code doesn't matter. But if you have multiple assignments to the same signal in a process, the last assignment wins. 

--- Quote End ---  

 

Thank you. That's what I need.
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