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Altera_Forum
Honored Contributor I
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cyclone v, addr in FPGA DDR to cl_mem

Hello,  

We use Cyclone V and 2 DDR, one DDR is connected to hps(HPS_DDS) and second connected to FPGA part (FPGA_DDR). 

We have VHDL core for grab frame(image) from camera into FPGA_DDR. 

We have OpenCL kernel for process frame, where parameter zero is pointer to frame. 

How i can convert addr in FPGA_DDR(frame_addr) to cl_mem(or some other) for call clSetKernelArg(kernel,0,&mem,sizeof(mem)) ? 

(when i try 

uint32_t frame_addr = 0x400000; 

clSetKernelArg(kernel,0,&frame_addr,sizeof(frame_addr)) 

host program segfault in# 0 0xb5a236ec in acl_mem_is_valid () from /tftpboot/boot/opencl/arm32/lib/libalteracl.so# 1 0xb5a1924a in clSetKernelArgAltera () from /tftpboot/boot/opencl/arm32/lib/libalteracl.so  

)
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