Need to write timing constraints for PLL generated clocks?

[Altera_Forum]

Dear all, 

 I managed to write an SDC file for the external clock with:  create_clock -period 40.00 -name {CLK_25MHz} [get_ports {CLK_25MHz}]  This clock is the input of a PLL that generated 3 clocks at 25, 50 and 100 MHz. Do I have to specify these clocks in the SDC file? How?  I found some documentation, but did not manage to write a valid constraint  http://quartushelp.altera.com/16.1/index.htm#mapidtopics/jka1465597353763.htm  Additionally I have the following: Warning (332056): PLL cross checking found inconsistent PLL clock settings:  Warning (332056): Node: UclocksLVDS|clocklvds_25_100mhz_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] was found missing 1 generated clock that corresponds to a base clock with a period of: 40.000  Is there a tool in the GUI to edit timing constraints?  Cyclone V: 5CEBA9F31C8, Quartus Prime 16.1.1 Build 200 11/30/2016 SJ Lite Edition.

[Altera_Forum]

create_clock -period 40.00 -name {CLK_25MHz} [get_ports {CLK_25MHz}] 

derive_pll_clocks  That is most likely it. If you want to cut timing between any clocks, let's say the 50MHz and 100MHz are related but the 25MHz is not, then find the names of the three generated clocks(just run Report Clocks in TimeQuest), and add the following: set_clock_groups -asynchronous -group {pll_50mhz_name pll_100mhz_name}   -group {pll_25mhz_name}  Most likely all three clocks are related, but just showing it as an example. If just starting .sdc constraints, the following might be of interest: http://www.alterawiki.com/wiki/timequest_user_guide

[Altera_Forum]

Thanks a lot! 

Indeed all three clocks are related. I have a new world to discover! (I am new to Altera)

[Altera_Forum]

Dear all, 

 It worked well (at least in Quartus, the board is not designed yet). Then I added one external 48 MHz clock that is not related to the others, and I could write the constraint  set_clock_groups -asynchronous -group {CLK_48MHz }   -group {UclocksLVDS|clocklvds_25_100mhz_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk UclocksLVDS|clocklvds_25_100mhz_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}  It worked well. But now I have five external clocks and four PLLs, and I do not manage to correctly write the SDC file. My source file contains:     LesPLLs25MHz : for i in CLK_25MHz'range generate UclocksLVDS : component clockLVDS_25_100MHz             port map (                 refclk => CLK_25MHz(i),                 rst => RESET, -- '0',                 outclk_0 => clk_coeur(i),                 outclk_1 => clk_x4(i),                 outclk_2 => open, -- clk_x2(i),                 locked => pll_lock(i)             );   end generate; [/INDENT]   And I have tried to write:  set_clock_groups -asynchronous -group {CLK_48MHz }   -group { \LesPLLs25MHz:0:UclocksLVDS|clocklvds_25_100mhz_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk               \LesPLLs25MHz:0:UclocksLVDS|clocklvds_25_100mhz_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk }   -group { \LesPLLs25MHz:1:UclocksLVDS|clocklvds_25_100mhz_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk               \LesPLLs25MHz:1:UclocksLVDS|clocklvds_25_100mhz_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk }   -group { \LesPLLs25MHz:2:UclocksLVDS|clocklvds_25_100mhz_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk               \LesPLLs25MHz:2:UclocksLVDS|clocklvds_25_100mhz_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk } \   -group { \LesPLLs25MHz:3:UclocksLVDS|clocklvds_25_100mhz_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk               \LesPLLs25MHz:3:UclocksLVDS|clocklvds_25_100mhz_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk }   But it is wrong: "Ignored filter at my_filename.sdc(13): ... could not be matched with a clock" Sometimes I also get <<invalid command name "-group">> Is it bad to use a vector/generate with clocks? I did not manage to use the signal names I choose in my source file ("clk_x4", ...).  I could start a new thread... Thank you in advance

[Altera_Forum]

First of all, what does your create_clock constraint look like for the new 48 MHz clock? Is "CLK_48MHz" what you have in the -name argument or is that the name of the clock in your HDL code? Next, if the 48 MHz domain should be separated from all other clock domains, you could simply say: 

 set_clock_groups -asynchronous -group CLK_48MHz  Having only one -group isolates that clock from all others.

[Altera_Forum]

"CLK_48MHz" is the name in my HDL code. Indeed, the 48MHz clock is independent from all others, but also each 25 MHz clock is independent from the other. It is a bit uncommon, but we will use several 25 MHz (programmable) oscillator on the same board to simulate several boards with several oscillator. Do I have to define (slightly) different period for each 25 MHz clock? 

 My SDC file contains: create_clock -period 20.833 -name {CLK_48MHz} [get_ports {CLK_48MHz}]  create_clock -period 40.00 -name {CLK_25MHz[0]} [get_ports {CLK_25MHz[0]}] create_clock -period 40.00 -name {CLK_25MHz[1]} [get_ports {CLK_25MHz[1]}] create_clock -period 40.00 -name {CLK_25MHz[2]} [get_ports {CLK_25MHz[2]}] create_clock -period 40.00 -name {CLK_25MHz[3]} [get_ports {CLK_25MHz[3]}] derive_pll_clocks  set_clock_groups -asynchronous -group {CLK_48MHz } \ ... ...and then I have problems

[Altera_Forum]

I'm willing to bet that vectorizing the clocks is the issue ([0],[1], etc.). Each clock should have a unique name and not be vectorized.

[Altera_Forum]

Well, it seems I mainly have syntactic issues. With your help I could make it work with a unique name for each clock, but then it worked also with a vector of clocks. One point is that after the '\' at the end of the line, no space character is allowed. It is useful to "Read SDC File" in TimeQuest, but only possible when the design Fit is complete... 

 Thanks a lot