Hi, I use the IEEE.numeric_std.all Library for programming in VHDL. When the programcode consits a comparison between unsigned and integer the syntax checker tell that all is ok an the code compiles an synthesized also with Mentors ModelSim. But when i ask for the FSM-Graph via State Machine Viewer the field is empty and the Viewer doesen´t show the graph. The State Machine Viewer can´t handle this comparision but quartusII compiles and synthesize the code and the code works on hardware. Greez Dustin
