CDC-50001 - 1-Bit Asynchronous Transfer Not Synchronized

[OrF]

I'm trying to re-open this ticket  - I didn't found how , 

but anyway I tried to change the default Quartus SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 (instead of 3) 

and still get the same warning , any way to debug it ? 

https://community.intel.com/t5/Intel-Quartus-Prime-Software/CDC-50001-1-Bit-Asynchronous-Transfer-Not-Synchronized/m-p/1609971

[ShengN_Intel]

Hi Or,

Sure. Let me know if you have any further concern or update.

[OrF]

Bottom line: After all the trial and error in these threads, I need to do two things:

1.Set the global assignment with -name SYNCHRONIZER_IDENTIFICATION "FORCED IF ASYNCHRONOUS".
2.Remove the reset from the synchronizers.

But I’m wondering if this is a bug in Quartus or if there’s a technical explanation for why this is necessary.

Regarding the synchronizer, in ASIC design, synchronizers do have an async reset.

What about FORCED IF ASYNCHRONOUS?

Thanks,
Or

[ShengN_Intel]

Hi Or,

Sometimes the flip-flop with async clear will not be identified as synchronizer due to other considerations of the tool. Some of the reasons mentioned before. If that happens, try to avoid async clear. You'll find that the synchronizer template code all without the async clear.

[OrF]

thanks 

what about the meaning , FORCED IF ASYNCHRONOUS ? or why cant I use the Forced option 

[ShengN_Intel]

Hi Or,

Those flip-flop with async clear can't be identified as synchronizer even after enable FORCED IF ASYNCHRONOUS means can't be forced. This is the tool consideration for the functionality. In this case, better avoid the async clear.

Thanks,

Regards,

Sheng