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Hi again!
I get an error when tying to compile with the flag -c: aoc -v -c cluster_k.cl then: Internal Error: DSP Builder for Intel(R) FPGAs - Advanced Blockset Internal Restriction: 'm_startVec.size() > 0' in commonBackend::EnumerateLatencyConstraints::Private::beginSetIteration at p4/ip/aion/src/mip_common/latency_constraint_iterator.cpp:268. Error: DSP Builder for Intel(R) FPGAs - Advanced Blockset Internal Restriction: 'm_startVec.size() > 0' in commonBackend::EnumerateLatencyConstraints::Private::beginSetIteration at p4/ip/aion/src/mip_common/latency_constraint_iterator.cpp:268. the line that is causing this error is: b2 = ceil(components * tolerance); components is an integer that is incremented through a loop, tolerance is a constant double. Whats the problem with the above line? (Also b2 is integer) Thanks in advanceLink Copied
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This looks like a bug in the compiler. Try the latest version of Quartus, v17.1. If you still got the same error, open a support ticket with Altera and report it.
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--- Quote Start --- This looks like a bug in the compiler. Try the latest version of Quartus, v17.1. If you still got the same error, open a support ticket with Altera and report it. --- Quote End --- from the specification, they say that the return value and arguments must be of the same type.. https://www.khronos.org/registry/opencl/sdk/2.0/docs/man/xhtml/ceil.html So i changed it and no problem. Thanks HRZ :cool:
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Excuse me, could you tell me how to open a support ticket with Altera? I met a same question with you.
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Excuse me, could you tell me how to open a support ticket with Altera? I met a same question whether Quartus 16.0 or 17.0 can solve the error.
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--- Quote Start --- Excuse me, could you tell me how to open a support ticket with Altera? I met a same question whether Quartus 16.0 or 17.0 can solve the error. Thank you very much! --- Quote End --- Go to altera.com, create an account, log in, and open a service request.

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