Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
17268 Discussions

CSI-2 transmitter

Altera_Forum
Honored Contributor II
‎04-24-2018 12:17 PM
1,468 Views

Does anyone have a project with a CSI-2 transmitter? 

For example, on 10M50 eval board. 

Because no matter how hard we try, mistakes always occur: 

 

Error: Pin "TX_HS_CP" requires a pseudo-differential I/O assignment. 

or 

Error: Can't place node "TX_HS_CP" -- node is a differential I/O node 

or 

Error: Can't place differential I/O pins and/or associated SERDES transmitters or receivers -- location assignments are illegal 

Error: Pin "TX_HS_CP" with Differential 1.8-V HSTL Class I I/O standard must be driven by the external clock output of an enhanced PLL 

 

Need help
0 Kudos

Link Copied

0 Replies
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.