Can I safely ignore these hierarchy connectivity warnings?

Altera_Forum · ‎03-14-2018

Hello, I have the following problem that I have not been able to solve by searching the Forums:

I have a system with a Nios2 gen2 processor and the nios_custom_instr_floating_point custom instruction. This is the only custom instruction IP used.

On compilation I get the warning "1 hierarchies have connectivity warnings - see the Connectivity Checks report folder"

When I check the Connectivity Checks report I see the following 3 warnings (I include the reset_req Info for completeness):

Port                    Type    Severity    Details
reset_req                Input    Info        Stuck at GND
A_ci_multi_estatus    Output    Warning        Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.
A_ci_multi_ipending    Output    Warning        Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.
A_ci_multi_status        Output    Warning        Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.

I don't know how to determine if these signals are really needed in the design or have been left unconnected because they are not needed.

Does anybody know if I can safely ignore them and why?

Altera_Forum · ‎03-14-2018

You can safely ignore them if you know those ports are not needed in your design, along with the logic that drives them.

Otherwise you will need to investigate why they are not connected

Altera_Forum · ‎03-15-2018

Thank you for the prompt answer Tricky.

I have investigated but I can not determine if these signals are needed or not. They don't appear anywhere in the source code. I know these output signals are missing from the cpu (nios ii gen 2) instance because the Connectivity Warning appears related to this instance and also in the RTL viewer I can find several signals with name A_ci_multi.... coming out of the nios ii instance. As the warning messages say the missing signals will appear in the entity code for the nios ii cpu, but this code is encripted.

I also can not find any reference to these signals in any documentation so I think I have reached as far as I can for myself. I think the only thing left to do is ask Altera support directly.

Altera_Forum · ‎03-15-2018

You'll have to get used to these kinds of warnings. Altera (and Xilinx) IP cores will throw thousands of warnings like this - and because you just have to trust their IP, you generally have to put up with it!