Can I write, compile and simulate VHDL code by using only modelSim?

[TarikTec]

I just started learning using Quartus Prime Standard and I find it taking too much time each time I want to modify the VHDL code in Quartus ,then compile then simulate using the modelSim.

is there a possibility of Using only in the development phase the ModelSim while I can modify the TestBench and the Source code on the same window?

[sstrell · Accepted solution]

Unless you're doing a gate-level simulation that requires device timing delays, you don't need to compile in Quartus at all before running a simulation in ModelSim.  Quartus can generate simulation scripts for you (for compiling in Modelsim, setting up the waveform view, etc.), but you don't even need to do that.

At a minimum, you might want to run Analysis & Elaboration in Quartus to verify syntax and connectivity, but other than that, you don't need to compile any further before simulating.

[Kenny_Tan]

you may take a look on this https://www.youtube.com/watch?v=o2KDwNN5-yw as well.

[Kenny_Tan]

any further queries?

[TarikTec]

No further queries from this question(I will post in another thread the other quation). thank you

[Kenny_Tan]

we shall close this thread. If you still need further assistance, you are welcome to post a response within 15days or open a new thread, some one will be right with you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.