I have a Cyclone IV design with 3 ROMs in it. Each ROM is 256 words by 256 bits. After I compile the design the RTL netlist viewer shows all 3 ROMs and the compilation report shows that the memory resources for all 3 ROMs was used. If I look for the ROM outputs with the Quartus node finder I can see the ROM outputs, all 256 of them, for each ROM. I do this in the post-compilation view, so I know these nets are in there and didn't get merged or dropped.
The problem is that in the timing analyzer only a few of the ROM outputs can be found and for one of the three ROMs nothing at all can be found. If I add a reference to the missing ROM in the SDC file the timing analyzer flags it as an error because it can't find that ROM.
Has anyone had a similar problem with the timing analyzer? Is this a known bug?
What options are you using in Report Timing to try to find the nets? Is your design fully constrained for timing with a .sdc file (clocks and I/O at a minimum)?
The only options I'm using in Report Timing are the "from" clock and "To" clocks, "Setup" is selected, "Detail level" is "Full path". In the Targets section, I then click the From search button.
In the Name Finder that pops up, I select get_pins and a filter of *rom*. My ROMs have instance names of rom0, rom1 and rom2. When I click the List button I get the data outputs for rom0 and rom1 and nothing for rom2. I should see 256 data outputs for each ROM, but I only get the outputs for rom0 and rom1.
Yes, I have my SDC file setup with clocks and I/O ports.
Where is the output of that third ROM going? Other logic or to output pins? There must be something incorrect in your filtering for the report to not be seeing these paths.
I presume you are using the post-fit (Standard edition) or final (Pro) timing netlist.
All three ROMs are at the start of very similar signal chains, only the ROM contents are different. I'm using the ROMs without an output register and they all parallel load some shift registers.
Yes, I'm using the post-fit timing netlist. Like I said, the Quartus Node Finder finds the ROM outputs for all 3 ROMs in the post-fit netlist.
Try turning on the Hierarchical option in the Name Finder. Without that, wildcards only search the current hierarchical level you've specified (you'd have to do something like *|*|* etc. to search further down). It looks like that 3rd ROM might be further down in the hierarchy.
With Hierarchical on, Compatibility mode gets turned off and wild cards don't work. But if I clear the filter and select get_pins it seems to list all pins in the design in alphabetical order. Still no rom2.
In any case, all 3 ROMs are in the same Verilog module and therefore should be at the same hierarchical level.
Wildcards don't work? I've never had that issue with hierarchical. Wildcards are the main point behind that option, so I'm not sure why it's not working for you. What exactly happens when you use a wildcard?
The only other thing I can think of is an issue with the timing netlist. Try deleting and recreating the timing netlist manually in the Timing Analyzer. You might even want to try a full recompile of the design. It doesn't make sense that a whole bunch of nets are visible in tools like the Tech Map Viewer (Node Finder) and not in the Timing Analyzer (Name Finder).
In the Name Finder Hierarchical and Compatibility Mode are mutually exclusive, one or the other is always checked but not both. With Hierarchical checked wildcards don't work, it finds nothing if there is anything other than one *.
I deleted everything in the project, databases, etc., just left the source files, qip files and the qpf and qsf files. Recompiled and rom2 still isn't seen by the timing analyzer.
The reason this is a problem is because all 3 ROMs need multicycle timing constraints. I can't add the multicycle constraint for rom2 because the timing analyzer thinks it doesn't exist. So I don't know if the design is being properly analyzed or constrained. If a major piece of the design isn't being analyzed then the compiled results can't be relied on to be correct.
I'm using Quartus Lite 20.1.1. I checked the Quartus download webpage this morning and 20.1.1 is the latest available download. I checked again TA name finder with the same results as before, please see attached screen shots. I also attached the fitter RAM summary report that shows that all three ROMs in the design post-fit.
Project QAR is attached.
Steps to reproduce:
- Compile project with Quartus 20.1.1 (Build 720 11/11/2020 SJ Lite Edition)
- Open Timing Analyzer
- In Timing Analyzer: create timing netlist, read SDC file, update timing net list
- In Timing Analyzer: View->Name Finder...
- In Name Finder: Set collection to get_pins
- In Name Finder: Set filter to *rom0* and click "List" button
- Note that pins for rom0 are shown
- Change filter to *rom2* and click "List" button
- Note that no pins are shown and "No matches found" is displayed.
- In Quartus main window compilation report: Fitter->Resource Section->RAM Summary
- Note that rom0, rom1 and rom2 are all present
Additional note: In the Quartus main window, using View->Utility Windows->Node Finder and selecting the "Pins: all & Registers: post-fitting" filter produces similar results, i.e. rom0 and rom1 can be found but not rom2.
I can reproduce the issue. Seem this Quartus Standard is also affected by this. In TMV post fit as well, filter for pin rom0 and rom1 can be searched but not rom2. I will forward this to developer and probably will take sometime due to legacy device. I will put this to close pending and you may create new case refer to this case asking for update.
Thanks for looking into this. I don't know what you mean by "create a new case", there is no way of creating support cases with Intel. I had to call Intel corporate to get this issue escalated and I just got lucky.