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17268 Discussions

Can't generate .vo file

Altera_Forum
Honored Contributor II
2,384 Views

Hi, 

 

My design includes a fir filter generated using fir_compiler 3.3.1.  

I want to generate the .vo file of this design and do function simulation in modelsim.  

 

When doing the complete compilation, analysis & synthesis, fitter ,assembler and classic timing analysis are all OK. But the EDA Netlist Writer fails and can't generate this .vo file . The error is " Can't generate netlist output files because the file "C:/altera/megacore/fir_compiler-v3.3.1/lib/tdl_da_lc.v" is an OpenCore Plus time-limited file". 

 

How to solve it ? 

 

Thanks! 

Tigre
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Altera_Forum
Honored Contributor II
1,532 Views

If this IP doesn't support try-before-you-buy simulation, then you have to pay for a license. You can use the OpenCore .sof file to try out the IP in hardware without a license.

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Altera_Forum
Honored Contributor II
1,532 Views

who knows the meaning of these equations which has been written in .vo file? 

please help me. I have no idea about LCELL and CARRY! 

 

\Mult0|auto_generated|le3a [0] = LCELL(\Mult0|auto_generated|cs1a [0] $ (\A~combout [7] & \Mult0|auto_generated|cs2a [0])) 

 

\comp1|LessThan0~47COUT1_98 = CARRY(\A~combout [1] & \B~combout [1] & !\comp1|LessThan0~52COUT1_96 # !\A~combout [1] & (\B~combout [1]# !\comp1|LessThan0~52COUT1_96 )) 

 

Thanks
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Altera_Forum
Honored Contributor II
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The said LCELL and CARRY are the real gate-level entities used in Altera FPGAs. You can read a functional description in the designing with low-level primitives user guide http://www.altera.com/literature/ug/ug_low_level.pdf. The logic expressions are generic ABEL, their meaning is obvious to my opinion, cause ony NOT, AND, OR and XOR are used from of the ABEL operators.

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Altera_Forum
Honored Contributor II
1,532 Views

HI, 

 

where I can find the precedence of these operators? 

 

Thanks
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Altera_Forum
Honored Contributor II
1,532 Views

There are ABEL references at the internet. E.g. http://www.seas.upenn.edu/~ese201/abel/abel_primer.html

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Altera_Forum
Honored Contributor II
1,532 Views

Dear Fvm!, 

Thanks for your very useful help. I have another question :) 

Is there any way to extract the gate-level netlist of synthesized behavioral verilog code in Quartus or Xilinx ISE? 

 

Thank U so much.
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