Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Can we constrain a fix delay time from pin to several nodes?

Altera_Forum
Honored Contributor II
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Hi Dears: 

 

As the title, i want to drive a pin to 3 node in my FPGA. Can i set a constrain that the delay time from the pin to these 3 node are same? If can, how to set? 

 

Thanks in advance!
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