Chip planner

[ymiler]

Hi

I'd like to know how can I know how many resources exist in region lock that I choosen ?

The property tab includes wrong values of DSP / M20K 

Do you have any user guide for it ?

[sstrell]

You're saying you created a Logic Lock region and the region properties are incorrect?  How do you know they are wrong?  Screenshot of what you're seeing?

[ymiler]

example 1:

I choose randomly region as "test" name:

the resources are:

example 2 :

I moved the region lock to another place where some of the resources are occupied:

But the logic lock region properties tab show same utilization of resources even though part of them is occupied. 

[sstrell]

You have to create a region then compile the project for this to show information about resources used in the region.  Just creating the region without assigning logic to it and not compiling doesn't do or show anything.  What's your goal here?

[ymiler]

I'd like to assign logic elements (ALM, DSP, memories) to a region lock,

but I don't know if the location has enough space for all the logic elements.

My question is: How can I obtain this information?

As I mentioned previously, the information about the region is incorrect.

[ymiler]

Hi

More questions ,

can you explain the innfo about the M20K below :

and what about another screenshot:

How can I have -3 ALM ???

same question about the percentage:

[SyafieqS]

You can simply create logic lock region and assign them in module wise in hierarchy tab. Concern on not enough space for all the module intended in the region, you can easily enlarge it (i cant remembered but somewhere is region lock window). And regarding this information of the module in region locked you must compile first, only then fitter will assigned (forced the logic locked in this region) and able to see the resource used in the region locked. Regarding the picture attached with weird value for m20k and alm, to me seem something is not correct with Quartus information on this. What version are you using?

[ymiler]

You can simply create logic lock region and assign them in module wise in hierarchy tab. Concern on not enough space for all the module intended in the region. - How can I know if there is enough space for all the module ? I don't have this information - Quartus doesn't show me this info. 

What version are you using? - version 22.3

[sstrell]

This is the trickiest aspect to floorplanning a design.  First, you have to ask yourself, do I really have to floorplan?  Remember that floorplanning limits the placement options for the Fitter, so it can adversely affect the performance of your design.  If you absolutely need to floorplan, like for a design flow like Partial Reconfiguration, the best thing to do is first do a compilation of your design with no Logic Lock regions at all.  You can then cross probe from the Project Navigator hierarchy view to the Chip Planner to highlight in color the resources used to implement different parts of the design.  Based on that, you should be able to create an LL region with the appropriate size and location to contain whatever entity/entities you want to assign to it.  After you create the region and assign the logic, recompile to see if the logic was able to be placed in the region.  You'll get a no fit if it wasn't.

[SyafieqS]

Yes it is true from what sstrell was saying. From my experience this all like a floor planning. What I did is, I will compile first, in chip planner after compilation, you will the module being placed in chip, you can differentiate the module by colors, and from that you can estimate how large your logic lock is needed.

[ymiler]

Hi

I'd like to understand what size of LL I should select. Is there an option in the "Chip Planner" tool to determine whether my selection (logic lock) is smaller or larger?

My design includes a lot of logic elements, I don't want to wait 10 hours to know if there is enough space in the LL area.

[sstrell]

Again, you can use the compilation without LL regions as a guide.  You could also create your LL region as unlocked/floating, allowing the Fitter to select a size and location for the region.  You can then customize the resulting Fitter-created region based on this result (which you would want to do because the Fitter will only make it big enough to contain the assigned logic).

[ymiler]

OK

Thank you. 

what about my previous question:

I get information about the region lock from the chip planner, but it seems that something wrong with the data.  

can you explain the info about the M20K below:

and what about another screenshot:

How can I have -3 ALM ???

same question about the percentage:

Quartus version 22.3

[SyafieqS]

Did this information pop up after you compile the logic with logic locked assigned?

[ymiler]

No,

I got this info when I draw region lock .

[SyafieqS]

As I said, the information supposed to be treated after you have your logic lock with the logic in it compiled.

That how the report is tabulated.