Using the Clock Control IP in the Stratix 10 as a clock gating controller with one clock input. The clock enable is in Distributed Sector Level and Negative Latch mode.
Quartus Prime Version 18.1.0 Build 09/21/2018 SJ Pro Edition.
If the design is limited in size, it does seem to be able to compile without issue. But once we run the full design, which takes up about 40% of a Stratix 10, then the crash occurs during the fitter stage. The pop-up box to send a report to Intel does come up, and I do send it to Intel.
Compile effort is Balanced, although I have seen the same issue with some of the Performance switches turned on.
Commenting out the Clock Control IP and using the non gated clock, no issue with compiling is found.