Compilation error

[Fernand_a]

During the compilation of my project, I had the following message:

"Error (275021): Illegal wire or bus name" "of type signal"

I'm a beginner in the software and I'm not sure what to do to fix this problem. I understand that the error is due to an illegal name of a wire, since I did not use buses in my project. But since I have hundreds of wires in my project I could not identify the troubling one, and I'm also not sure what "type signal" means.

The images attached don't give a very good view of the project, but the file is also bellow.

I apreciate any kind of help!

Fernanda

[sstrell]

Double-click any error in the Messages window to take you to where the error is located.  Since you're using a schematic, it could be some wire stub that is connected incorrectly.

Highly recommended to learn an HDL like Verilog or VHDL instead of continuing to do schematic design.  You can convert your schematics to HDL from the File menu in Quartus, which would help you to learn it.

[Fernand_a]

Thank you for the answer!

Unfortunately when I double-clicked the error it didn't take me anywhere, I also tried to right click and press Locate in Design File but the result was the same. Is there another way to find where the error is?

[sstrell]

If that's the case, you'll just need to check through wires manually.  The report says the error is in SAP1pR, so you'll need to look through that schematic to find a stray or incorrectly connected wire.

[Fernand_a]

There are thousands of wires in the schematic, that make this task really hard, but I'll try.

Appreciate your help!

[KennyTan_Altera]

Which device and Quartus version that you were using?

My suggestion is to convert the schematic to Verilog files, but keep in mind that this feature is only available in the Quartus Standard Edition.

You can use Quartus to convert your schematic (.bdf) into Verilog — where the tool can actually pinpoint the bad signal name.

1. In Quartus, go to: File > Create/Update > Create HDL Design File from Current File
2. Choose:

• Output format: Verilog HDL
• Input file: your .bdf top-level file

1. Click OK.

Quartus will generate a .v (Verilog) file containing all the wiring and module definitions from your schematic.

You can use this Verilog file to debug more easily and quickly narrow down which signal name is causing the problem.

Alternatively, you may want to start converting everything to Verilog or VHDL, as schematic entry is a feature that Altera has begun deprecating.

[Fernand_a]

I'm using a regular Dell notebook with windows 10 and I tried to run on Quartus Prime Lite 20.1 and Quartus Prime Standart 24.1 but the error was the same in both.
Since the scheme won't compile properly, I can't generate a Verilog file.
Appreciate your help!

[FvM · Accepted solution]

Hi,
schematic entry is really legacy and has many trapdoors. As suggested, it would be a good idea to switch to HDL entry.

You managed to type space as connector name somewhere in the schematic. Best way to find such errors to open .bdf file in text editor and search for illegal " " name. You'll find this connector (connection wire) entry.

(connector
	(text " " (rect 2504 846 2521 848)(font "Intel Clear" )(vertical))
	(pt 2520 864)
	(pt 2520 784)
)

 Simply delete line starting with "(text" and save.

Alternatively use the xy coordinates to navigate to the element in schematic editor and correct therein.

Regards

Frank

[Fernand_a]

Hi, Frank!
I deeply appreciate your help. I could solve the problem and compile successfully.

Thank you very much!
Fernanda

[KennyTan_Altera]

I’m glad that your question has been addressed, we shall close this thread.