Compile a design from a copy of its qsys

[anonimcs]

Hi all,

I want to use a qsys file that is mostly a copy of a previous version of the same project. I have a design that I can synthesize and implement on an Arria10 FPGA but due to obsolescence of a memory component I had to modify my design accordingly. So I have copied the qsys file (and stored it in another directory than my workspace for a backup) and renamed it. Then I opened the new qsys file in Platform Designer (I'm using Quartus 17.1 Standard version btw) and changed the ddr4 settings of the project and then generated HDL (ended with no errors). Then I compiled my design and got an error message at the Place and Route phase regarding the EMIF IP's that's generated by Altera considering my qsys file. I got the following error message but not sure what's wrong here as I would not expect an Altera IP not being found, especially given that I can successfully implement my design with the source (old) qsys file of the design.

Any help would be appreciated!

Cheers,

Info (332104): Reading SDC File: 'max_SOM12/altera_emif_arch_nf_171/synth/max_SOM12_altera_emif_arch_nf_171_lgjq4ha.sdc' Info (332151): Clock uncertainty is not calculated until you update the timing netlist. Critical Warning: get_entity_instances : Could not find any instances of entity max_SOM12_altera_emif_arch_nf_171_lgjq4ha Error: The auto-constraining script was not able to detect any instance for core < max_SOM12_altera_emif_arch_nf_171_lgjq4ha > Error: Make sure the core < max_SOM12_altera_emif_arch_nf_171_lgjq4ha > is instantiated within another component (wrapper) Error: and it's not the top-level for your project Critical Warning (332008): Read_sdc failed due to errors in the SDC file

[sstrell]

You don't mention anything about the creation of a new project that uses this copy of the .qsys which I presume you did.  In the new project settings, make sure the correct design files have been added to the project, including this .qsys (or the .qip created when you generated the system; you can only add one or the other).

It might have been easier to do a project copy from the Project menu and then make changes as needed to the copy of the existing project instead of bringing over just this one file.

[anonimcs]

Because I didn't create a new project, I'm trying to use the copied qsys file for the already-existing project, so I don't have new qpf/qsf etc. In the project settings, I had already made sure that the new qsys was added to the project, but apparently that was not the root cause of the issue I'm having here

[Nurina]

Hi,

Does the above comment help?

Regards,

Nurina

[sstrell]

I don't understand.  So you already had a second project and you copied this .qsys file into its project directory?  And then added the .qsys file to this second project's design files (Project menu -> Add remove/files)?

You then opened the .qsys from the already open project, regenerated the system (which completed successfully), and then compiled the project, which is when you got the errors.

Or are you saying that you opened a .qsys for an IP (not an entire system design) and did this?  What exactly is in this .qsys file that you copied?

Long story short, there is most likely a path or other file association issue here.

[anonimcs]

Sorry for not making it clear from the start, I had one project and a qsys file for that. I copied that qsys file so that I could play around with it and go back any time I wanted by simply using the original one. I renamed the new qsys and opened it with the Platform Designer, made a few changes, and then generated HDL so that I could use the new one for my project (there is no new project, I only have 1 qpf file). Synthesis was successful with the new one but it fails at Fitter stage. I double-checked and the new qsys is added as a project file, so not sure what the problem is here

[sstrell]

Is the .qsys your top-level design or are you instantiating the system in a higher-level design?

What files are listed under Add/Remove files and in the Timing Analyzer settings (.sdc files)?

[anonimcs]

The qsys belongs to the top-level.

I have no files listed in the sdc file, just setting constraints and setting clock groups for the IPs used within the project. Under Add/remove Files, the following are listed: some qsys files for the IPs used in the project, 2 qip files for the IP's that are bought from other companies, top-level VHDL file, the sdc file.

[Nurina]

Hi,

Can you share the .qar file of your project here so I can see how you are doing this?

To generate this, go to Project>Archive Project.

Regards,

Nurina

[anonimcs]

I cannot share the project files, they're confidential

[Nurina]

Hi,

Any updates?

[Nurina]

Hi,

Since there is no feedback for this thread, I shall set this thread to a close pending. If you need further assistance, you are welcome to re-open this case within 20 days or open a new case and someone will help you.

If you happen to close this case you will receive a survey. If you think you would rank your support experience less than 4 out of 5, please allow me to correct it before closing or if the problem can't be corrected, please let me know the cause so that I may improve your future experience.

p/s: If any answer from the Intel Support is helpful, please feel free to provide rating with 4/5 survey on the support provided.

Thanks,

Best regards,

Nurina