Compiling VHLD file in quartus

[KenCiszewski]

I have been learning about quartus using

https://www.allaboutcircuits.com/projects/from-vhdl-code-to-real-hardware-designing-a-finite-state-machine/.

There's a VHDL file that I compiled in quartus for the EPM240 FPGA see attached. For a while it compiled correctly, eventually I got all kinds of error messages.

I compiled as Verilog HDL and VHDL, for a while it was fine as Verilog HDL, but eventually wouldn't compile. 

Any thoughts?

[FvM]

Hi,
forgot to tell the error messages.

[FvM]

The original VHDL file compiles without problems in Quartus 13.1. It should be however noted, that the default "one-hot" state encoding leads to a very inefficient counter implementation in 27 logic elements. Specifying sequential encoding, e.g. using synthesis attribute reduces resource utilization to 6 LE.

[ShengN_Intel]

The file had been compiled in VHDL without any problem as mentioned.