Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Ankündigungen
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
17268 Diskussionen

Connect Bus Line to another Bus Line

Altera_Forum
Geehrter Beitragender II
3.877Aufrufe

http://www.alteraforum.com/forum/attachment.php?attachmentid=12167&stc=1  

 

I am doing universal shift register in quartus. The situation now is I want to connect Q[0] to data1[1], Q[1] to data1[2],... and so on. Is it possible to do that?
0 Kudos
4 Antworten
Altera_Forum
Geehrter Beitragender II
2.456Aufrufe

Yes. Correct a net to q[0] and label it data1[1].

Altera_Forum
Geehrter Beitragender II
2.456Aufrufe

 

--- Quote Start ---  

Yes. Correct a net to q[0] and label it data1[1]. 

--- Quote End ---  

 

 

Is this what u mean? 

http://www.alteraforum.com/forum/attachment.php?attachmentid=12170&stc=1  

 

I got error for this. Error: Can't find name for bus. Q and data1 bus is impossible to have same name.
Altera_Forum
Geehrter Beitragender II
2.456Aufrufe

 

--- Quote Start ---  

Yes. Correct a net to q[0] and label it data1[1]. 

--- Quote End ---  

 

 

Is this what u mean? 

https://www.alteraforum.com/forum/attachment.php?attachmentid=12171  

 

I got error for this. Error: Can't find name for bus. Q and data1 bus is impossible to have same name as it represent different things.
Altera_Forum
Geehrter Beitragender II
2.456Aufrufe

Dont connect it - because you're connecting a single bit to a 5 bit bus. 

You just leave the connection disconnected and leave it to connect via named association - as you have with D0, D1 etc.
Antworten